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High-Level VLSI SynthesisJanuary 1991
- Editors:
- Raul Camposano,
- Wayne H. Wolf
Abstract
No abstract available.
Cited By
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- Yang L and Muzio J Keynote speech Proceedings of the First international conference on Embedded Software and Systems, (15-24)
- Wang W, Jha N, Raghunathan A and Dey S High-level Synthesis of Multi-process Behavioral Descriptions Proceedings of the 16th International Conference on VLSI Design
Wong J, Megerian S and Potkonjak M Forward-looking objective functions Proceedings of the 39th annual Design Automation Conference, (904-909)- Ramanujam J, Deshpande S, Hong J and Kandemir M A Heuristic for Clock Selection in High-Level Synthesis Proceedings of the 2002 Asia and South Pacific Design Automation Conference
- Narasimhan N, Teica E, Radhakrishnan R, Govindarajan S and Vemuri R (2019). Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis, Formal Methods in System Design, 19:3, (237-273), Online publication date: 1-Oct-2001.
- Kao P, Hsieh C and Wu A An RTL design-space exploration method for high-level applications Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (162-168)
- Gupta S, Savoiu N, Dutt N, Gupta R and Nicolau A Conditional speculation and its effects on performance and area for high-level snthesis Proceedings of the 14th international symposium on Systems synthesis, (171-176)
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- Mansouri N and Vemuri R (2000). Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs, Formal Methods in System Design, 16:1, (59-91), Online publication date: 1-Jan-2000.
- Dey S, Raghunathan A and Wagner K (1998). Design for Testability Techniques at the Behavioraland Register-Transfer Levels, Journal of Electronic Testing: Theory and Applications, 13:2, (79-91), Online publication date: 1-Oct-1998.
- Ashar P, Bhattacharya S, Raghunathan A and Mukaiyama A Verification of RTL generated from scheduled behavior in a high-level synthesis flow Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (517-524)
- Juan H, Gajski D and Chaiyakul V Clock-driven performance optimization in interactive behavioral synthesis Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (154-157)
- Blumenröhr C and Eisenbiegler D An efficient representation for formal synthesis Proceedings of the 10th international symposium on System synthesis, (9-15)
- Govindarajan S and Vemuri R Cone Based Clustering for List Scheduling Algorithms Proceedings of the 1997 European conference on Design and Test
- Wilberg J and Camposano R (1997). VLIW Processor Codesign for Video Processing, Design Automation for Embedded Systems, 2:1, (79-119), Online publication date: 1-Jan-1997.
- Lee M, Hsu Y, Chen B and Fujita M (1997). Domain---Specific High---Level Modeling and Synthesis for ATM Switch Prototyping, Design Automation for Embedded Systems, 2:3-4, (319-338), Online publication date: 1-May-1997.
- Dawid H, Koch K and Stahl J ADPCM codec Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
- Chang J and Pedram M Energy minimization using multiple supply voltages Proceedings of the 1996 international symposium on Low power electronics and design, (157-162)
- Narasimhan N, Vemuri R and Roy J Synchronous Controller Models for Synthesis from Communicating VHDL Processes Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
- Chiodo M, Guisto P, Jurecska A, Lavagno L, Sentovich E, Hsieh H, Suzuki K and Sangiovanni-Vincentelli A Synthesis of software programs for embedded control application Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (587-592)
- Ecker W Semi-dynamic scheduling of synchronization-mechanisms Proceedings of the conference on European design automation, (374-379)
- Frank E and Lengauer T APPlaUSE Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (662-667)
- Razdan R and Smith M A high-performance microarchitecture with hardware-programmable functional units Proceedings of the 27th annual international symposium on Microarchitecture, (172-180)
- Kission P, Ding H and Jerraya A Structured design methodology for high-level design Proceedings of the 31st annual Design Automation Conference, (466-471)
- Both A, Biermann B, Lerch R, Manoli Y and Sievert K Hardware-software-codesign of application specific microcontrollers with the ASM environment Proceedings of the conference on European design automation, (72-76)
- Ramachandran L, Gajski D, Narayan S, Vahid F and Fung P 100-hour design cycle Proceedings of the conference on European design automation, (144-149)
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- Wilberg J, Camposano R and Rosenstiel W Design flow for hardware/software cosynthesis of a video compression system Proceedings of the 3rd international workshop on Hardware/software co-design, (73-80)
- Gajski D and Ramachandran L (1994). Introduction to High-Level Synthesis, IEEE Design & Test, 11:4, (44-54), Online publication date: 1-Oct-1994.
- Aas E, Steen T and Klingsheim K (1994). Quantifying Design Quality Through Design Experiments, IEEE Design & Test, 11:1, (27-38), Online publication date: 1-Jan-1994.
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- Wehn N, Herpel H, Hollstein T, Poechmueller P and Glesner M High-level synthesis in a rapid-prototype environment for mechatronic systems Proceedings of the conference on European design automation, (188-193)
- Ramachandran L, Vahid F, Narayan S and Gajski D Semantics and synthesis of signals in behavioral VHDL Proceedings of the conference on European design automation, (616-621)
- Ku D, Filo D and De Micheli G Control optimization based on resynchronization of operations Proceedings of the 28th ACM/IEEE Design Automation Conference, (366-371)
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