article

The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication

Authors:

David I. August,

Wen-Mei W. Hwu,

Scott A. MahlkeAuthors Info & Claims

International Journal of Parallel Programming, Volume 27, Issue 5

Pages 381 - 423

https://doi.org/10.1023/A:1018787007582

Published: 01 October 1999 Publication History

Abstract

Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involves converting program control flow into conditional, or predicated, instructions. This process is known as if-conversion. In order to apply ifconversion effectively, one must address two major issues: what should be ifconverted and when the if-conversion should be performed. A compiler's use of predication as a representation is most effective when large amounts of code are if-converted and when if-conversion is performed early in the compilation procedure. On the other hand, efficient execution of code generated for a processor with predicated execution requires a delicate balance between control flow and predication. The appropriate balance is tightly coupled with scheduling decisions and detailed processor characteristics. This paper presents a compilation framework based on partial reverse if-conversion that allows the compiler to maximize the benefits of predication as a compiler representation while delaying the final balancing of control flow and predication to schedule time.

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Cited By

Nuzman DZaks ABen-Zion ZRodríguez GSadayappan PSukumaran-Rajam A(2024)If-Convert as Early as You MustProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641562(26-38)Online publication date: 17-Feb-2024
https://dl.acm.org/doi/10.1145/3640537.3641562
Jordan AKim NKrall ABrandner FAa T(2013)IR-level versus machine-level if-conversion for predicated architecturesProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443611(3-10)Online publication date: 24-Feb-2013
https://dl.acm.org/doi/10.1145/2443608.2443611
Connors DGrover ECaldwell B(2013)Exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systemsProceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2432516.2432519(1-8)Online publication date: 21-Jan-2013
https://dl.acm.org/doi/10.1145/2432516.2432519
Show More Cited By

Index Terms

The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems

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Information

Published In

cover image International Journal of Parallel Programming

International Journal of Parallel Programming Volume 27, Issue 5

Oct. 1999

99 pages

ISSN:0885-7458

Editors:
Utpal Banerjee
Intel Corp., Santa Clara, CA
,
Nicholas Carriero
Yale Univ., New Haven, CT
,
Wen-Mei Hwu
Univ. of Illinois at Urbana-Champaign, Urbana
,
Alex Nicolau
Univ. of California-Irvine, Irvine

Issue’s Table of Contents

Copyright © Copyright © 1999 Plenum Publishing Corporation.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 1999

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Cited By

Nuzman DZaks ABen-Zion ZRodríguez GSadayappan PSukumaran-Rajam A(2024)If-Convert as Early as You MustProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641562(26-38)Online publication date: 17-Feb-2024
https://dl.acm.org/doi/10.1145/3640537.3641562
Jordan AKim NKrall ABrandner FAa T(2013)IR-level versus machine-level if-conversion for predicated architecturesProceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems10.1145/2443608.2443611(3-10)Online publication date: 24-Feb-2013
https://dl.acm.org/doi/10.1145/2443608.2443611
Connors DGrover ECaldwell B(2013)Exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systemsProceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2432516.2432519(1-8)Online publication date: 21-Jan-2013
https://dl.acm.org/doi/10.1145/2432516.2432519
Maher BSmith ABurger DMcKinley K(2006)Merging Head and Tail Duplication for Convergent Hyperblock FormationProceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2006.34(65-76)Online publication date: 9-Dec-2006
https://dl.acm.org/doi/10.1109/MICRO.2006.34

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