article

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend

Authors:

Tuomas Korhonen,

Kari A. I. HalonenAuthors Info & Claims

Analog Integrated Circuits and Signal Processing, Volume 37, Issue 3

Pages 201 - 213

https://doi.org/10.1023/A:1026269725649

Published: 01 December 2003 Publication History

Abstract

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-μm BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.

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Cited By

Boni AAzzolini CVecchi DChiorboli G(2018)Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCsCircuits, Systems, and Signal Processing10.1007/s00034-008-9094-z28:4(487-504)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s00034-008-9094-z

Index Terms

A Self-Calibrated Pipeline ADC with 200 MHz IF-Sampling Frontend
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
  2. Emerging technologies

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Published In

cover image Analog Integrated Circuits and Signal Processing

Analog Integrated Circuits and Signal Processing Volume 37, Issue 3

December 2003

134 pages

ISSN:0925-1030

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Copyright © Copyright © 2003 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 01 December 2003

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Cited By

Boni AAzzolini CVecchi DChiorboli G(2018)Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCsCircuits, Systems, and Signal Processing10.1007/s00034-008-9094-z28:4(487-504)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s00034-008-9094-z

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