research-article

Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems

Authors:

Alice C. ParkerAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 678 - 690

https://doi.org/10.1109/12.2206

Published: 01 June 1988 Publication History

Abstract

The effect of clocking schemes on overlapped execution performance in a digital system is described and quantified. Effects of branching, data dependencies, and resource conflicts between consecutive tasks are considered. Some problems of clocking scheme synthesis for the design of digital systems with maximum execution overlap are examined. Effects of performance of the choice of clocking scheme, partitioning of functions into the time steps, the number of clock phases, the length of each phase (i.e., how to pipeline), and the assignment of functions to clock phases are treated.

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Cited By

Ishii ALeiserson CPapaefthymiou M(1997)Optimizing two-phase, level-clocked circuitryJournal of the ACM10.1145/256292.25630144:1(148-199)Online publication date: 15-Jan-1997
https://dl.acm.org/doi/10.1145/256292.256301
DeCastelo-Vide-e-Souza YPotkonjak MParker APreas B(1995)Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retimingProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217516(113-118)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217516
Potkonjak MRabaey J(1994)Optimizing throughput and resource utilization using pipeliningJournal of VLSI Signal Processing Systems10.5555/204140.28131958:2(117-130)Online publication date: 1-Oct-1994
https://dl.acm.org/doi/10.5555/204140.2813195

Index Terms

Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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Copyright © Copyright © 1988 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 June 1988

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Cited By

Ishii ALeiserson CPapaefthymiou M(1997)Optimizing two-phase, level-clocked circuitryJournal of the ACM10.1145/256292.25630144:1(148-199)Online publication date: 15-Jan-1997
https://dl.acm.org/doi/10.1145/256292.256301
DeCastelo-Vide-e-Souza YPotkonjak MParker APreas B(1995)Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retimingProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217516(113-118)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217516
Potkonjak MRabaey J(1994)Optimizing throughput and resource utilization using pipeliningJournal of VLSI Signal Processing Systems10.5555/204140.28131958:2(117-130)Online publication date: 1-Oct-1994
https://dl.acm.org/doi/10.5555/204140.2813195

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