research-article

A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases

Authors:

I. S. Hsu,

T. K. Truong,

L. J. Deutsch,

I. S. ReedAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 735 - 739

https://doi.org/10.1109/12.2212

Published: 01 June 1988 Publication History

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Abstract

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained.

References

[1]

{1} E. R. Berlekamp, "Bit-serial Reed-Solomon encoders," IEEE Trans. Inform. Theory, vol. IT-28, pp. 869-874, Nov. 1982.

Google Scholar

[2]

{2} C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, "VLSI architecture for computing multiplications and inverses in GF(2<sup>m</sup>)," IEEE Trans. Comput., vol. C-34, Aug. 1985.

Crossref

Google Scholar

[3]

{3} P. A. Scott, S. E. Tarvares, and L. E. Peppard, "A fast multiplier for GF(2<sup>m</sup>)," IEEE J. Select. Areas Commun., vol. SAC-4, Jan. 1986.

Google Scholar

[4]

{4} I. S. Hsu, I. S. Reed, T. K. Truong, K. Wang, C. S. Yeh, and L. J. Deutsch, "The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm," IEEE Trans. Comput., vol. C-33, Oct. 1984.

Google Scholar

[5]

{5} H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder," IEEE Trans. Comput., vol. C-34, May 1985.

Google Scholar

[6]

{6} M. Perlman and J. J. Lee, "A comparison of conventional Reed-Solomon encoders and Berlekamp's architecture," NASA Tech. Brief 3610-81-119, Jet Propulsion Lab., Pasadena, CA, July 10, 1981.

Google Scholar

[7]

{7} C. C. Wang, "Computer simulation of finite field multiplications based on Massey-Omura's normal basis representation of field elements," private communication, 1985.

Google Scholar

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A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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IEEE Computer Society

United States

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Published: 01 June 1988

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