research-article

Strongly Code Disjoint Checkers

Authors:

M. Nicolaidis,

B. CourtoisAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 751 - 756

https://doi.org/10.1109/12.2217

Published: 01 June 1988 Publication History

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Abstract

Strongly code-disjoint (SCD) checkers are defined and shown to include totally self-checking (TSC) code-disjoint checkers. This type of checker is the natural companion of strongly fault-secure (SFS) networks. SCD checkers are the largest class of checkers with which a combinational system may achieve the TSC goal. Some examples are given to illustrate the design of SCD checkers.

References

[1]

{1} D. A. Anderson, "Design of self-checking digital networks using coding techniques," Rep. 527, CSL/Univ. Illinois, Sept. 1971.

Google Scholar

[2]

{2} J. M. Ashjaee and S. M. Reddy, "On totally self-checking checkers for separable codes," in Proc. 6th FTCS, Pittsburgh, PA, June 21-23, 1976.

Google Scholar

[3]

{3} W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," in Proc. IFIP Congress, Edinburgh, 1968, Inf. Processing 68, Amsterdam, North Holland, 1969.

Google Scholar

[4]

{4} B. Courtois, "Failure mechanisms, fault hypotheses and analytical testing on LSI NMOS (HMOS) circuits," in Proc. VLSI 81, Univ. Edinburgh, 1981.

Google Scholar

[5]

{5} J. Galiay, Y. Crouzet, M. Vergniault, "Physical versus logical fault models MOS LSI circuits: Impact on their testability," IEEE Trans. Comput., June 1980.

Google Scholar

[6]

{6} I. Jansch and B. Courtois, "Design of checkers based on analytical fault hypotheses," in Proc. 20th Euro. Solid-State Circuits Conf., Edinburgh, Scotland, Sept. 1984.

Google Scholar

[7]

{7} J. P. Khakbaz and E. J. McCluskey, "Self testing embedded parity checkers exaustive XOR gate testing," Stanford Univ., CRC Rep. 82- 10/CSL TN 207, June 1982.

Google Scholar

[8]

{8} J. P. Mak, J. A. Abraham, and E. S. Davidson, "The design of PLAs with concurrent error detection," in Proc. 12th FTCS, Santa Monica, CA, June 22-24, 1982.

Google Scholar

[9]

{9} McCluskey and F. W. Clegg, "Fault equivalence in combinational logic networks," IEEE Trans. Comput., vol. C-20, pp. 1286-1293, Nov. 1971.

Google Scholar

[10]

{10} M. Nicolaidis, I. Jansch, and B. Courtois, "Strongly code disjoint checkers," in Proc. 14th FTCS, Orlando, FL, June 1984.

Google Scholar

[11]

{11} M. Nicolaidis, "An unified BIST approach using specific strongly code disjoint checkers design," IMAG Rep. 599, Mar. 1986.

Google Scholar

[12]

{12} J. E. Smith and G. Metze, "Strongly fault secure logic networks," IEEE Trans. Comput., June 1978.

Google Scholar

[13]

{13} J. Viaud and R. David, "Sequentially self-checking circuits," in Proc. FTCS 10, June 1980, pp. 263-268.

Google Scholar

[14]

{14} J. P. Wakerly, "Partially self-checking circuits and their use in performing logical operations," IEEE Trans. Comput., July 1974.

Google Scholar

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Strongly Code Disjoint Checkers

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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IEEE Computer Society

United States

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Published: 01 June 1988

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Omaña MFiore AMetra CFanucci LTeich J(2016)Inverters' self-checking monitors for reliable photovoltaic systemsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971964(672-677)Online publication date: 14-Mar-2016
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Cox AMohanram KRixner STorrellas J(2006)Dependable ≠ unaffordableProceedings of the 1st workshop on Architectural and system support for improving software dependability10.1145/1181309.1181318(58-62)Online publication date: 21-Oct-2006
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Metra CFavalli MDi Francescantonio SRiccò B(2002)On-Chip Clock Faults' DetectorJournal of Electronic Testing: Theory and Applications10.1023/A:101657023020518:4-5(555-564)Online publication date: 1-Aug-2002
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Kavousianos XNikolos D(1999)Modular TSC Checkers for Bose-Lin and Bose CodesProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836496Online publication date: 26-Apr-1999
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Metra CFavalli MRiccò B(1998)On-line detection of logic errors due to crosstalk, delay, and transient faultsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745605(524-533)Online publication date: 18-Oct-1998
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