research-article

Aliasing Probability for Multiple Input Signature Analyzer

Authors:

D. K. Pradhan,

S. K. Gupta,

M. G. KarpovskyAuthors Info & Claims

IEEE Transactions on Computers, Volume 39, Issue 4

Pages 586 - 591

https://doi.org/10.1109/12.54855

Published: 01 April 1990 Publication History

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Abstract

Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q-ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q-ary codes (q=2/sup m/, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given.

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 39, Issue 4

April 1990

188 pages

ISSN:0018-9340

Editor:
Ming T. Liu
Ohio State Univ., Columbus

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IEEE Computer Society

United States

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Published: 01 April 1990

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Zgheib APotin ORigaud JDutertre J(2023)A CCFI Verification Scheme Based on the RISC-V Trace EncoderConstructive Side-Channel Analysis and Secure Design10.1007/978-3-031-29497-6_3(42-61)Online publication date: 3-Apr-2023
https://dl.acm.org/doi/10.1007/978-3-031-29497-6_3
Hadjicostis C(2005)Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test VectorsIEEE Transactions on Computers10.1109/TC.2005.18954:12(1614-1627)Online publication date: 1-Dec-2005
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Abdulla MRavikumar CKumar A(1999)Built-in Self Test Based on Multiple On-Chip Signature CheckingJournal of Electronic Testing: Theory and Applications10.1023/A:100831020379014:3(227-244)Online publication date: 1-Jun-1999
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Elsaholy MShaheen SSeireg R(1998)A Unified Analytical Expression for Aliasing Error Probability Using Single-Input External- and Internal-XOR LFSRIEEE Transactions on Computers10.1109/12.73768747:12(1414-1417)Online publication date: 1-Dec-1998
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Savir J(1996)Reducing the MISR SizeIEEE Transactions on Computers10.1109/12.53623545:8(930-938)Online publication date: 1-Aug-1996
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Iwasaki KNakamura S(1996)Aliasing Error for a Mask ROM Built-In Self-TestIEEE Transactions on Computers10.1109/12.48556645:3(270-277)Online publication date: 1-Mar-1996
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Gupta SPradhan D(1996)Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice VersaIEEE Transactions on Computers10.1109/12.48148745:1(63-73)Online publication date: 1-Jan-1996
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Fujiwara TFeng SKasami TIwasaki K(1995)On the Maximum Value of Aliasing Probabilities for Single Input Signature RegistersIEEE Transactions on Computers10.1109/12.47512244:11(1265-1274)Online publication date: 1-Nov-1995
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An analysis of the aliasing probability of multiple-input signature registers in the case of a 2^m-ary symmetric channel