research-article

On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays

Authors:

H. M. Shao,

I. S. ReedAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 10

Pages 1273 - 1280

https://doi.org/10.1109/12.5988

Published: 01 October 1988 Publication History

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Abstract

A novel VLSI design for a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous study is replaced by a time-domain algorithm through a detailed comparison of their VLSI implementations. An architecture that implements the time-domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using multiplexing technique, an implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Some improvements result in both enhanced capability and significant reduction in silicon area, making it possible to build the decoder on a single chip.

References

[1]

{1} H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder," IEEE Trans. Comput., vol. C-34, May 1985.

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{2} R. P. Brent and H. T. Kung, "Systolic VLSI arrays for polynomial GCD computations," Dep. Comput. Sci., Carnegie-Melon Univ., Pittsburgh, PA, Rep., 1982.

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{3} H. M. Shao, T. K. Truong, J. S. Hsu, L. J. Deutsch, and I. S. Reed, "A single chip VLSI Reed-Solomon decoder," Jet Propulsion Lab. TDA Progress Rep. 42-84, Oct.-Dec. 1985.

Google Scholar

[4]

{4} I. S. Reed, T. K. Truong, and R. L. Miller, "Decoding of BCH and RS codes with errors and erasures using continued fractions," Electron. Lett., July 1979.

Crossref

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{5} W. L. Eastman, private communication, MITRE Corp., Apr. 1986.

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{6} R. J. McEliece, The Theory of Information and Coding, Reading, MA: Addison-Wesley, 1977.

Digital Library

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{7} E. R. Berlekamp, "Bit serial Reed-Solomon encoders," IEEE Trans. Inform. Theory, Nov. 1982.

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Samanta JBhaumik JBarman S(2017)FPGA based area efficient RS(23, 17) codecMicrosystem Technologies10.1007/s00542-016-3058-123:3(639-650)Online publication date: 1-Mar-2017
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Baek JSunwoo M(2013)New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon DecodersJournal of Signal Processing Systems10.1007/s11265-012-0692-471:2(159-168)Online publication date: 1-May-2013
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Lee SKumar B(2010)Pattern-flipping chase-type decoders with error pattern extracting viterbi algorithm over partial response channelsIEEE Journal on Selected Areas in Communications10.5555/1734877.173488328:2(181-187)Online publication date: 1-Feb-2010
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On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 10

October 1988

165 pages

ISSN:0018-9340

Editor:
Ming T. Liu

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IEEE Computer Society

United States

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Published: 01 October 1988

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Samanta JBhaumik JBarman S(2017)FPGA based area efficient RS(23, 17) codecMicrosystem Technologies10.1007/s00542-016-3058-123:3(639-650)Online publication date: 1-Mar-2017
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Baek JSunwoo M(2013)New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon DecodersJournal of Signal Processing Systems10.1007/s11265-012-0692-471:2(159-168)Online publication date: 1-May-2013
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Yuan BWang ZLi LGao MSha JZhang C(2009)Area-efficient Reed-Solomon decoder design for optical communicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2009.202092856:6(469-473)Online publication date: 1-Jun-2009
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Shimizu KTogawa NIkenaga TGoto STang T(2005)Reconfigurable adaptive FEC system with interleavingProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121036(1252-1255)Online publication date: 18-Jan-2005
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Lee JLee JSunwoo M(2003)Design of application-specific instructions and hardware accelerator for reed-solomon codecsEURASIP Journal on Advances in Signal Processing10.1155/S11108657033091382003(1346-1354)Online publication date: 1-Jan-2003
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Lee H(2003)High-speed VLSI architecture for parallel Reed-Solomon decoderIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81078211:2(288-294)Online publication date: 1-Apr-2003
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Chang JChoi SLee M(2001)New Syndrome Check Error Estimation and Its Concatenated CodingWireless Personal Communications: An International Journal10.1023/A:101256850138219:3(193-204)Online publication date: 1-Dec-2001
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Shayan YLe-Ngoc T(1997)A Cellular Structure for a Versatile Reed-Solomon DecoderIEEE Transactions on Computers10.1109/12.55980546:1(80-85)Online publication date: 1-Jan-1997
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Zarowski C(1995)Parallel Implementation of the Schur Berlekamp-Massey Algorithm on a Linearly Connected Processor ArrayIEEE Transactions on Computers10.1109/12.39286244:7(930-933)Online publication date: 1-Jul-1995
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Modified Low-Complexity Chase Soft-Decision Decoder of Reed---Solomon Codes

Algebraic soft-decision decoder architectures for long Reed-Solomon codes

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