research-article

A Chip-Multiprocessor Architecture with Speculative Multithreading

Authors:

Venkata Krishnan,

Josep TorrellasAuthors Info & Claims

IEEE Transactions on Computers, Volume 48, Issue 9

Pages 866 - 880

https://doi.org/10.1109/12.795218

Published: 01 September 1999 Publication History

Abstract

Much emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in an application. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for speculative execution of sequential binaries without source recompilation. We present the software support that enables identification of threads from a sequential binary. The hardware includes a memory disambiguation mechanism that enables the detection of interthread memory dependence violations during speculative execution. This hardware is different from past proposals in that it does not rely on a snoopy-based cache-coherence protocol. Instead, it uses an approach similar to a directory-based scheme. Furthermore, the architecture includes a simple and efficient hardware mechanism to enable register-level communication between on-chip processors. Evaluation of this software-hardware approach shows that it is quite effective in achieving high performance when running sequential binaries.

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Cited By

Posluns GZhu YZhang GJeffrey MSalapura VZahran MChong FTang L(2022)A scalable architecture for reprioritizing ordered parallelismProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527387(437-453)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527387
Kumar SSingh SAggarwal NGupta BAlhalabi WBand S(2022)An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheadsInternational Journal of Intelligent Systems10.1002/int.2306237:12(11764-11790)Online publication date: 8-Sep-2022
https://dl.acm.org/doi/10.1002/int.23062
Saad MPalmieri RRavindran B(2019)LernaACM Transactions on Storage10.1145/331036815:1(1-24)Online publication date: 22-Mar-2019
https://dl.acm.org/doi/10.1145/3310368
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Index Terms

A Chip-Multiprocessor Architecture with Speculative Multithreading
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 48, Issue 9

September 1999

140 pages

ISSN:0018-9340

Editor:
Jean-Luc Gaudiot
Univ. of Southern California, Los Angeles

Issue’s Table of Contents

Copyright © Copyright © 1999 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 September 1999

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Cited By

Posluns GZhu YZhang GJeffrey MSalapura VZahran MChong FTang L(2022)A scalable architecture for reprioritizing ordered parallelismProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3527387(437-453)Online publication date: 18-Jun-2022
https://dl.acm.org/doi/10.1145/3470496.3527387
Kumar SSingh SAggarwal NGupta BAlhalabi WBand S(2022)An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheadsInternational Journal of Intelligent Systems10.1002/int.2306237:12(11764-11790)Online publication date: 8-Sep-2022
https://dl.acm.org/doi/10.1002/int.23062
Saad MPalmieri RRavindran B(2019)LernaACM Transactions on Storage10.1145/331036815:1(1-24)Online publication date: 22-Mar-2019
https://dl.acm.org/doi/10.1145/3310368
Zahran M(2019)Heterogeneous ComputingundefinedOnline publication date: 1-Mar-2019
Li LLi FShi GGeng K(2018)An Efficient Stream Data Processing Model for Multiuser Cryptographic ServiceJournal of Electrical and Computer Engineering10.1155/2018/39178272018Online publication date: 31-Jul-2018
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Saad MPalmieri RRavindran BBreitgand DYadgar GPorter DEyal I(2018)LernaProceedings of the 11th ACM International Systems and Storage Conference10.1145/3211890.3211897(37-48)Online publication date: 4-Jun-2018
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Irie HKoizumi TFukuda AAkaki SNakae SBessho YShioya RNotsu TYoda KIshihara TSakai SOskin MInoue K(2018)STRAIGHTProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00019(121-133)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00019
Li ZLiu LDeng YYin SWang YWei S(2017)Aggressive Pipelining of Irregular Applications on Reconfigurable HardwareACM SIGARCH Computer Architecture News10.1145/3140659.308022845:2(575-586)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080228
Li ZLiu LDeng YYin SWang YWei S(2017)Aggressive Pipelining of Irregular Applications on Reconfigurable HardwareProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080228(575-586)Online publication date: 24-Jun-2017
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(2017)Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architectureParallel Computing10.1016/j.parco.2017.07.00767:C(1-19)Online publication date: 1-Sep-2017
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