research-article

Pseudorandom Rounding for Truncated Multipliers

Authors:

N. Yoshida,

E. Goto,

S. IchikawaAuthors Info & Claims

IEEE Transactions on Computers, Volume 40, Issue 9

Pages 1065 - 1067

https://doi.org/10.1109/12.83650

Published: 01 September 1991 Publication History

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Abstract

An economical, unbiased, overflow-free rounding scheme for multiplication of multiple-precision floating-point numbers is proposed. The scheme, called pseudorandom rounding, saves multiplications of lower bits and makes use of statistical properties of bits around the least significant bit of products in order to compensate for truncated parts. The method is deterministic, and inputs are commutable. The validity of the rounding is verified by numerical simulation.

References

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{2} TRW LSI Multipliers Applications Notes, Redondo Beach, TRW LSI Products.

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{3} D. E. Knuth, The Art of Computer Programming, Vol. 2. Reading, MA: Addison-Wesley, 1981, pp. 238-250.

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{4} J. L. Barlow and E. H. Bareiss, "On roundoff error distributions in floating point and logarithmic arithmetic," Computing, vol. 34, pp. 325-347, 1985.

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{5} J. L. Barlow, "Probabilistic error analysis of floating point and CRD arithmetics," Ph.D. dissertation, Northwestern Univ., Evanston, IL, June 1981.

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{6} D. J. Kuck, D. S. Parker, Jr., and A. H. Sameh, "Analysis of rounding methods in floating-point arithmetic," IEEE Trans. Comput., vol. C-26, pp. 643-650, July-1977.

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{7} J. Bustoz, A. Feldstein, R. Goodman, and S. Linnainmaa, "Improved trailing digits estimates applied to optimal computer arithmetic," J. ACM, vol. 26, pp. 716-730, Oct. 1979.

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{8} A. H. Taub, Ed. John von Neumann Collected Works, Vol. 5. New York: Macmillan, 1963, p. 57.

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Cited By

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Chang CSatzoda R(2018)A low error and high performance multiplexer-based truncated multiplierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202732718:12(1767-1771)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2027327

Index Terms

Pseudorandom Rounding for Truncated Multipliers
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis
      1. Arbitrary-precision arithmetic
      2. Interval arithmetic

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 40, Issue 9

September 1991

99 pages

ISSN:0018-9340

Editor:
Earl Swartzlander
Univ. of Texas, Austin

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IEEE Computer Society

United States

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Published: 01 September 1991

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Chang CSatzoda R(2018)A low error and high performance multiplexer-based truncated multiplierIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202732718:12(1767-1771)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2027327

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Recommendations

Enhanced-functionality multipliers

Very-High Radix Division with Prescaling and Selection by Rounding

Fixed-width multipliers for the implementation of efficient digital FIR filters

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