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Precision Architecture

Published: 01 January 1989 Publication History

Abstract

The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined. Extendibility and longevity features are considered.

References

[1]
1. J.S. Birnbaum and W.S. Worley, Jr., "Beyond RISC: High-Precision Architecture," Hewlett-Packard J., Vol. 36, No. 8, Aug. 1985.
[2]
2. D. Patterson, "Reduced Instruction Set Computers," Comm. ACM, Vol. 28, No. 1, Jan. 1985, pp. 8-21.
[3]
3. J. Hennessy et al., "MIPS: A Microprocessor Architecture," Proc. Micro-15, IEEE, Oct. 1982.
[4]
4. M.J. Mahon et al., "Hewlett-Packard Precision Architecture: The Processor," Hewlett-Packard J., Vol. 37, No. 8, Aug. 1986, pp. 4-21.
[5]
5. K.W. Pettis and W.B. Buzbee, "Hewlett-Packard Precision Architecture Compiler Performance," Hewlett-Packard J., Vol. 38, No. 3, March 1987, pp. 29-35.
[6]
6. J.A. Lukes, "HP Precision Architecture Performance Analysis," Hewlett-Packard J., Vol. 37, No. 8, Aug. 1986, pp. 30-39.
[7]
7. R.B. Garner et al., "The Scalable Processor Architecture (Sparc)," Proc. 26th Compcon, 1988, pp. 278-283.
[8]
8. G. Radin, "The 801 Minicomputer," Proc. SIG Arch/SIGPlan Symp. Architectural Support for Programming Languages and Operating Systems, ACM, Palo Alto, Calif., March 1982, pp. 39-47.
[9]
9. W.D. Strecker, "VAX-11/780: A Virtual Address Extension to the DEC PDP-11 Family," Proc. NCCC, June 1978, pp. 967-980.
[10]
10. IBM System/370 Principles of Operation, Form No. GA22-7000, IBM, Poughkeepsie, N.Y., 1970.
[11]
11. J. Moussouris et al., "A CMOS RISC Processor with Integrated System Functions," Proc. 31st Compcon, March 1986, pp. 126-131.
[12]
12. D. Fotland et al., "Hardware Design of the First HP Precision Architecture Computers," Hewlett-Packard J., Vol. 38, No. 3, March 1987, pp. 4-17.
[13]
13. S. Mangelsdorf et al., "A VLSI Processor for HP Precision Architecture," Hewlett-Packard J., Vol. 38, No. 9, Sept. 1987, pp. 4-11.
[14]
14. A. Marston et al., "A 32b CMOS Single-Chip RISC Type Processor," Proc. IEEE Int'l Solid-State Circuits Conf., Feb. 1987, pp. 28-29.

Cited By

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  • (2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
  • (2008)Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity MicroprocessorsJournal of Signal Processing Systems10.1007/s11265-008-0212-853:1-2(145-169)Online publication date: 1-Nov-2008
  • (2003)Architectural techniques for accelerating subword permutations with repetitionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81231811:3(325-335)Online publication date: 1-Jun-2003
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Reviews

Edward W. Davis

This well-written paper (in terms of both clarity of presentation and the value of the ideas) provides a description of an architecture developed by Hewlett-Packard that is in use in commercial products. The paper emphasizes design decisions in support of goals such as scalability, price-performance advantages, extensibility, and architectural longevity. As an example of a longevity feature, the precision architecture has a 64-bit virtual address range composed of 32-bit address spaces. Implementations are defined with different numbers of these spaces. Another interesting feature is the provision for instruction set extensions through an assists architecture in which the processor and memory interface is defined, but the function is left for future definition with execution on optional hardware. The paper is certainly readable by most people who are interested in computer architecture. It references several other sources for more detailed information.

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Published In

cover image Computer
Computer  Volume 22, Issue 1
January 1989
87 pages
ISSN:0018-9162
Issue’s Table of Contents

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 1989

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Cited By

View all
  • (2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
  • (2008)Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity MicroprocessorsJournal of Signal Processing Systems10.1007/s11265-008-0212-853:1-2(145-169)Online publication date: 1-Nov-2008
  • (2003)Architectural techniques for accelerating subword permutations with repetitionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81231811:3(325-335)Online publication date: 1-Jun-2003
  • (2001)Cryptography Efficient Permutation Instructions for Fast SoftwareIEEE Micro10.1109/40.97775921:6(56-69)Online publication date: 1-Nov-2001
  • (1999)Locking with Different Granularities for Reads and Writes in an MVM SystemProceedings of the 1999 International Symposium on Database Engineering & Applications10.5555/850953.853911Online publication date: 2-Aug-1999
  • (1999)Concurrent Event Handling through MultithreadingIEEE Transactions on Computers10.1109/12.79522048:9(903-916)Online publication date: 1-Sep-1999
  • (1999)Functional Implementation Techniques for CPU Cache MemoriesIEEE Transactions on Computers10.1109/12.75265148:2(100-110)Online publication date: 1-Feb-1999
  • (1997)VLIW Processor Codesign for Video ProcessingDesign Automation for Embedded Systems10.1023/A:10088187117862:1(79-119)Online publication date: 1-Jan-1997
  • (1996)64-bit and Multimedia Extensions in the PA-RISC 2.0 ArchitectureProceedings of the 41st IEEE International Computer Conference10.5555/792769.793625Online publication date: 25-Feb-1996
  • (1996)PA7300LC Integrates Cache for Cost/PerformanceProceedings of the 41st IEEE International Computer Conference10.5555/792769.793623Online publication date: 25-Feb-1996
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