research-article

Reducing Contention in Shared-Memory Multiprocessors

Author:

Per StenströmAuthors Info & Claims

Computer, Volume 21, Issue 11

Pages 26 - 37

https://doi.org/10.1109/2.86784

Published: 01 November 1988 Publication History

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Abstract

The techniques that can be used to design a memory system that reduces the impact of contention are examined. To exemplify the techniques, the implementations and the design decisions taken in each are reviewed. The discussion covers memory organization, interconnection networks, memory allocation, cache memory, and synchronization and contention. The multiprocessor implementations considered are C.mmp, CM*, RP3, Alliant FX, Cedar, Butterfly, SPUR, Dragon, Multimax, and Balance.

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Cited By

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Neilforoshan M(2005)Synchronization and cache coherence in computer designJournal of Computing Sciences in Colleges10.5555/1089053.108910421:2(341-348)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.5555/1089053.1089104
Dandamudi S(1997)Reducing Run Queue Contention in Shared Memory MultiprocessorsComputer10.1109/2.57367330:3(82-89)Online publication date: 1-Mar-1997
https://dl.acm.org/doi/10.1109/2.573673
Babuška IElman HMarkley K(1992)Parallel Implementation of the $hp$-Version of the Finite Element Method on a Shared-Memory ArchitectureSIAM Journal on Scientific and Statistical Computing10.1137/091308113:6(1433-1459)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.1137/0913081
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Index Terms

Reducing Contention in Shared-Memory Multiprocessors

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Reviews

Reviewer: Nigel Peter Topham

This paper, a useful introduction to the problem of contention in shared-memory multiprocessors, presents some of the solutions that have been adopted in real machines. While it is unlikely that researchers in the area of parallel architectures will find anything new here, the paper is well written and well structured and will benefit people to whom parallel architecture is a new concept. The author first considers interconnection mechanisms, memory allocation, and caching and synchronization issues. He goes on to describe, in general terms, the structure of such representative systems as CM*, RP3, the Alliant FX/8, Cedar, the BBN Butterfly, SPUR, Dragon, and the Sequent and Encore machines. If you teach computer architecture at the undergraduate level this paper is probably worth bringing to the attention of your students, though I would have preferred a more comprehensive list of references for this purpose. If you have a dormant interest in parallel machines, you will probably find this paper informative and easy to read.

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Published In

Computer Volume 21, Issue 11

November 1988

78 pages

ISSN:0018-9162

Editor:
Bruce D. Shriver
Univ. of Hawaii

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 November 1988

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Neilforoshan M(2005)Synchronization and cache coherence in computer designJournal of Computing Sciences in Colleges10.5555/1089053.108910421:2(341-348)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.5555/1089053.1089104
Dandamudi S(1997)Reducing Run Queue Contention in Shared Memory MultiprocessorsComputer10.1109/2.57367330:3(82-89)Online publication date: 1-Mar-1997
https://dl.acm.org/doi/10.1109/2.573673
Babuška IElman HMarkley K(1992)Parallel Implementation of the $hp$-Version of the Finite Element Method on a Shared-Memory ArchitectureSIAM Journal on Scientific and Statistical Computing10.1137/091308113:6(1433-1459)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.1137/0913081
Hartman JSanders D(1991)Teaching a course in parallel processing with limited resourcesACM SIGCSE Bulletin10.1145/107005.10702323:1(97-101)Online publication date: 1-Mar-1991
https://dl.acm.org/doi/10.1145/107005.107023
Hartman JSanders DDale N(1991)Teaching a course in parallel processing with limited resourcesProceedings of the twenty-second SIGCSE technical symposium on Computer science education10.1145/107004.107023(97-101)Online publication date: 1-Mar-1991
https://dl.acm.org/doi/10.1145/107004.107023
Anderson EBai ZDongarra JGreenbaum AMcKenney ADu Croz JHammarling SDemmel JBischof CSorensen DPryor DMontry GMartin J(1990)LAPACKProceedings of the 1990 ACM/IEEE conference on Supercomputing10.5555/110382.110385(2-11)Online publication date: 12-Nov-1990
https://dl.acm.org/doi/10.5555/110382.110385
Stenström P(1990)A Survey of Cache Coherence Schemes for MultiprocessorsComputer10.1109/2.5549723:6(12-24)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1109/2.55497
Stenström P(1989)A cache consistency protocol for multiprocessors with multistage networksACM SIGARCH Computer Architecture News10.1145/74926.7497117:3(407-415)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/74926.74971
Stenström PSyre J(1989)A cache consistency protocol for multiprocessors with multistage networksProceedings of the 16th annual international symposium on Computer architecture10.1145/74925.74971(407-415)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/74925.74971

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Recommendations

Reducing Hot-Spot Contention in Shared-Memory Multiprocessor Systems

Exploration of distributed shared memory architectures for NoC-based multiprocessors

Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors

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