research-article

Introducing the IA-64 Architecture

Authors:

Hans Mulder, and

Rumi ZahirAuthors Info & Claims

IEEE Micro, Volume 20, Issue 5

Pages 12 - 23

https://doi.org/10.1109/40.877947

Published: 01 September 2000 Publication History

Publisher Site

Abstract

Advances in microprocessor design, integrated circuits, and compiler technology have increased the interest in parallel instruction execution. The IA-64 processor instruction set architecture has been designed with parallelism in mind.

References

[1]

Intel IA-64 Architecture Software Developer's Manual, Vols. I-IV, Rev. 1.1, Intel Corp., July 2000; http://developer.intel.com.

Google Scholar

[2]

R.P. Colwell, et al., "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Trans. Computers, Aug. 1988, pp. 967-979.

Digital Library

Google Scholar

[3]

B.R. Rau, et al., "The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs," Computer, Jan. 1989, pp. 12-35.

Crossref

Google Scholar

[4]

S.A. Mahlke, et al., "Sentinel Scheduling for Superscalar and VLIW Processors," Proc. Fifth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, Oct. 1992, pp. 238-247.

Crossref

Google Scholar

[5]

D.M. Gallagher, et al., "Dynamic Memory Disambiguation Using the Memory Conflict Buffer," Proc. Sixth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, Oct. 1994, pp. 183-193.

Crossref

Google Scholar

[6]

J. Worley, et al., "AES Finalists on PA-RISC and IA-64: Implementations & Performance," Proc. The Third Advanced Encryption Standard Candidate Conf., NIST, Washington, D.C., Apr. 2000, pp. 57-74.

Google Scholar

[7]

S.A. Mahlke, et al., "A Comparison of Full and Partial Predicated Execution Support for ILP Processors," Proc. 22nd Int'l Symp. Computer Architecture, IEEE Computer Society Press, Los Alamitos, Calif., June 1995, pp. 138-150.

Crossref

Google Scholar

[8]

J. Bharadwaj, et al., "The Intel IA-64 Compiler Code Generator," Special Issue: Microprocessors of the 21st Century Part 2, Intel IA-64 Architecture, IEEE Micro, this issue.

Crossref

Google Scholar

Cited By

View all

Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614272
Zheng BYu CWang JDing YLiu YWang YPekhimenko G(2023)Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614248(1364-1380)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614248
Josipovic LGuerrieri AIenne PBazargan KNeuendorffer S(2019)Speculative Dataflow CircuitsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293914(162-171)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293914
Show More Cited By

Index Terms

Introducing the IA-64 Architecture
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Networks
  1. Network performance evaluation

Index terms have been assigned to the content through auto-classification.

Recommendations

The IA-64 Architecture at Work

Over the past several years, strategies to increase microprocessor performance have focused on finding more instruction-level parallelism. ILP is basically the idea of finding several instructions to execute at the same time. By providing multiple ...
Read More
An Advanced Optimizer for the IA-64 Architecture

The IA-64 architecture has a rich set of features including control and data speculation, predication, large register files, and an advanced branch architecture, which allow the compiler to exploit instruction-level parallelism (ILP) and optimize ...
Read More
The Intel IA-64 Compiler Code Generator

The IA-64 architecture was designed to allow the compiler to exploit a high level of instruction-level parallelism. Predication, control and data speculation, register rotation, loop branches, and a large register file are powerful features that the ...
Read More

Comments

Information & Contributors

Information

Published In

IEEE Micro Volume 20, Issue 5

September 2000

77 pages

ISSN:0272-1732

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 September 2000

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

42
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Other Metrics

View Author Metrics

Citations

Cited By

View all

Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614272
Zheng BYu CWang JDing YLiu YWang YPekhimenko G(2023)Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614248(1364-1380)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614248
Josipovic LGuerrieri AIenne PBazargan KNeuendorffer S(2019)Speculative Dataflow CircuitsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293914(162-171)Online publication date: 20-Feb-2019
https://dl.acm.org/doi/10.1145/3289602.3293914
Reed D(2014)Beowulf ClustersProceedings of the 20 Years of Beowulf Workshop on Honor of Thomas Sterling's 65th Birthday10.1145/2737909.2737913(28-33)Online publication date: 13-Oct-2014
https://dl.acm.org/doi/10.1145/2737909.2737913
Kim SDe Carli LSankaralingam KEstan CNajjar WYavatkar RRixner S(2013)SWSLProceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems10.5555/2537857.2537890(191-202)Online publication date: 21-Oct-2013
https://dl.acm.org/doi/10.5555/2537857.2537890
Kim YLee JMai TPaek Y(2012)Improving performance of nested loops on reconfigurable array processorsACM Transactions on Architecture and Code Optimization10.1145/2086696.20867118:4(1-23)Online publication date: 26-Jan-2012
https://dl.acm.org/doi/10.1145/2086696.2086711
Hennessy JPatterson D(2011)Computer Architecture, Fifth EditionundefinedOnline publication date: 29-Sep-2011
Chen HYuan LWu XZang BHuang BYew PAlbonesi DMartonosi MAugust DMartínez J(2009)Control flow obfuscation with information flow trackingProceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture10.1145/1669112.1669162(391-400)Online publication date: 12-Dec-2009
https://dl.acm.org/doi/10.1145/1669112.1669162
Stotzer ELeiss E(2009)Modulo scheduling without overlapped lifetimesACM SIGPLAN Notices10.1145/1543136.154245444:7(1-10)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1543136.1542454
Stotzer ELeiss EKirsch CKandemir M(2009)Modulo scheduling without overlapped lifetimesProceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1542452.1542454(1-10)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1542452.1542454
Show More Cited By

Abstract

References

Cited By

Index Terms

Recommendations

The IA-64 Architecture at Work

An Advanced Optimizer for the IA-64 Architecture

The Intel IA-64 Compiler Code Generator

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations