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research-article

Path sensitization in critical path problem [logic circuit design]

Published: 01 November 2006 Publication History

Abstract

An important aspect of the critical path problem is deciding whether a path is sensitizable. Three new path sensitization criteria are proposed in a general framework. Other path sensitization criteria can be presented in the same framework, enabling them to be compared with each other. An approximate criterion is also proposed and used to develop an efficient critical path algorithm for combinational circuits

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  • (2017)Hardware trojan detection based on correlated path delays in defiance of variations with spatial correlationsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130416(163-168)Online publication date: 27-Mar-2017
  • (2017)Path-Specific Functional Timing Verification under Floating and Transition Modes of OperationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062299(1-6)Online publication date: 18-Jun-2017
  • (2013)Sensitization criterion for threshold logic circuits and its applicationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561874(226-233)Online publication date: 18-Nov-2013
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  1. Path sensitization in critical path problem [logic circuit design]

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    cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 12, Issue 2
    November 2006
    177 pages

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    IEEE Press

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    Published: 01 November 2006

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    • (2017)Hardware trojan detection based on correlated path delays in defiance of variations with spatial correlationsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130416(163-168)Online publication date: 27-Mar-2017
    • (2017)Path-Specific Functional Timing Verification under Floating and Transition Modes of OperationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062299(1-6)Online publication date: 18-Jun-2017
    • (2013)Sensitization criterion for threshold logic circuits and its applicationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561874(226-233)Online publication date: 18-Nov-2013
    • (2013)Automatic test pattern generation for delay defects using timed characteristic functionsProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561848(91-98)Online publication date: 18-Nov-2013
    • (2012)Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay FaultsACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885117:4(1-20)Online publication date: 1-Oct-2012
    • (2012)Functional timing analysis made fast and generalProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228552(1055-1060)Online publication date: 3-Jun-2012
    • (2012)Unifying functional and parametric timing verificationProceedings of the great lakes symposium on VLSI10.1145/2206781.2206816(135-140)Online publication date: 3-May-2012
    • (2010)An efficient algorithm to verify generalized false pathsProceedings of the 47th Design Automation Conference10.1145/1837274.1837321(188-193)Online publication date: 13-Jun-2010
    • (2009)Efficient Boolean characteristic function for timed automatic test pattern generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201326928:3(417-425)Online publication date: 1-Mar-2009
    • (2008)Event propagation for accurate circuit delay calculation using SATACM Transactions on Design Automation of Electronic Systems10.1145/1255456.125547312:3(1-23)Online publication date: 22-May-2008
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