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A correctness criterion for asynchronous circuit validation and optimization

Published: 01 November 2006 Publication History

Abstract

In order to reasonably determine the correctness of asynchronous circuit implementations and specifications, Dill (1989) has developed a variant of trace theory. Trace theory describes the behavior of an asynchronous circuit by representing its possible executions as strings, called “traces.” A useful relation defined in this theory is called conformance, which holds when one trace specification can be safely substituted for another. We propose a new relation in the context of Dill's trace theory, called strong conformance. We show that this relation is capable of detecting certain errors in asynchronous circuits that cannot be detected through conformance. Strong conformance also helps to justify circuit optimization rules where a component is replaced by another component having extra capabilities (e.g., it can accept more inputs). The structural operators of Dill's trace theory-compose, rename, and hide-are shown to be monotonic with respect to strong conformance. Experiments are presented using a modified version of Dill's trace theory verifier that implements a check for strong conformance

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 13, Issue 11
November 2006
133 pages

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IEEE Press

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Published: 01 November 2006

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  • (2008)Pre-RTL formal verificationProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391675(806-811)Online publication date: 8-Jun-2008
  • (2003)Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous CircuitsProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009925Online publication date: 9-Nov-2003
  • (1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
  • (1998)Relative LivenessFormal Methods in System Design10.1023/A:100860201476612:1(73-115)Online publication date: 1-Jan-1998
  • (1996)Using Partial Orders For Trace Theoretic Verification Of Asynchronous CircuitsProceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems10.5555/785164.785217Online publication date: 18-Mar-1996
  • (1995)Hierarchical optimization of asynchronous circuitsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217616(712-717)Online publication date: 1-Jan-1995

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