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- Nelson CMyers CYoneda T(2003)Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous CircuitsProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009925Online publication date: 9-Nov-2003
- Beerel PBurch JMeng T(1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
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