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Optimum design of IC power/ground nets subject to reliability constraints

Published: 01 November 2006 Publication History

Abstract

The authors formulate and solve the problem of sizing power/ground (p/g) nets in integrated circuits composed of modules, where the nets are routed as trees in the channels between the modules. Constraints are developed to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule requirements. The objective is to minimize the area of the p/g nets subject to these constraints. An optimization technique tailored to this problem is developed. The technique solves the problem more efficiently than the steepest descent method and Newton's method. Several case studies are presented

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  • (2023)GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320639742:5(1662-1675)Online publication date: 1-May-2023
  • (2020)Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment WiresProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045673(74-79)Online publication date: 17-Jan-2020
  • (2018)Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wiresProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201706(399-404)Online publication date: 22-Jan-2018
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      cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 7, Issue 7
      November 2006
      93 pages

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      IEEE Press

      Publication History

      Published: 01 November 2006

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      View all
      • (2023)GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320639742:5(1662-1675)Online publication date: 1-May-2023
      • (2020)Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment WiresProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045673(74-79)Online publication date: 17-Jan-2020
      • (2018)Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wiresProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201706(399-404)Online publication date: 22-Jan-2018
      • (2018)Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2018.8297356(399-404)Online publication date: 22-Jan-2018
      • (2011)Reliability analysis and optimization of power-gated ICsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203626719:3(457-468)Online publication date: 1-Mar-2011
      • (2004)Efficient power/ground network analysis for power integrity-driven design methodologyProceedings of the 41st annual Design Automation Conference10.1145/996566.996617(177-180)Online publication date: 7-Jun-2004
      • (2004)Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimatesProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382625(479-484)Online publication date: 7-Nov-2004
      • (2002)Sizing Power/Ground Meshes for Clocking and Computing Circuit ComponentsProceedings of the conference on Design, automation and test in Europe10.5555/882452.874361Online publication date: 4-Mar-2002
      • (2001)RC Power Bus Maximum Voltage Drop in Digital VLSI CircuitsProceedings of the 2nd International Symposium on Quality Electronic Design10.5555/558593.850178Online publication date: 26-Mar-2001
      • (2001)Fast power/ground network optimization based on equivalent circuit modelingProceedings of the 38th annual Design Automation Conference10.1145/378239.379021(550-554)Online publication date: 22-Jun-2001
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