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Rotation scheduling: a loop pipelining algorithm

Published: 01 November 2006 Publication History

Abstract

We consider the resource-constrained scheduling of loops with interiteration dependencies. A loop is modeled as a data flow graph (DFG), where edges are labeled with the number of iterations between dependencies. We design a novel and flexible technique, called rotation scheduling, for scheduling cyclic DFGs using loop pipelining. The rotation technique repeatedly transforms a schedule to a more compact schedule. We provide a theoretical basis for the operations based on retiming. We propose two heuristics to perform rotation scheduling and give experimental results showing that they have very good performance

Cited By

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  • (2017)Optimal Functional-Unit Assignment for Heterogeneous Systems Under Timing ConstraintIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.267676428:9(2567-2580)Online publication date: 7-Aug-2017
  • (2015)Synthesis and Optimization of Pipelines for HW Implementations of Dataflow ProgramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.242727834:10(1613-1626)Online publication date: 1-Oct-2015
  • (2013)Allocating rotating registers by schedulingProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540738(346-358)Online publication date: 7-Dec-2013
  • Show More Cited By

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 16, Issue 3
November 2006
113 pages

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IEEE Press

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Published: 01 November 2006

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Cited By

View all
  • (2017)Optimal Functional-Unit Assignment for Heterogeneous Systems Under Timing ConstraintIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.267676428:9(2567-2580)Online publication date: 7-Aug-2017
  • (2015)Synthesis and Optimization of Pipelines for HW Implementations of Dataflow ProgramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.242727834:10(1613-1626)Online publication date: 1-Oct-2015
  • (2013)Allocating rotating registers by schedulingProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540738(346-358)Online publication date: 7-Dec-2013
  • (2013)Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloadsACM Transactions on Embedded Computing Systems10.1145/2423636.242364212:2(1-22)Online publication date: 22-Feb-2013
  • (2013)Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main MemoryJournal of Signal Processing Systems10.1007/s11265-012-0703-571:3(261-273)Online publication date: 1-Jun-2013
  • (2012)Cost Minimization with HPDFG and Data Mining for Heterogeneous DSPJournal of Signal Processing Systems10.1007/s11265-010-0546-x67:3(213-228)Online publication date: 1-Jun-2012
  • (2010)Iterational retiming with partitioningACM Transactions on Embedded Computing Systems10.1145/1698772.16987809:3(1-26)Online publication date: 5-Mar-2010
  • (2010)Dynamic and leakage energy minimization with soft real-time loop scheduling and voltage assignmentIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201094118:3(501-504)Online publication date: 1-Mar-2010
  • (2010)Energy-Aware Loop Parallelism Maximization for Multi-core DSP ArchitecturesProceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing10.1109/GreenCom-CPSCom.2010.87(205-212)Online publication date: 18-Dec-2010
  • (2010)Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad MemoryJournal of Signal Processing Systems10.1007/s11265-009-0362-358:2(247-265)Online publication date: 1-Feb-2010
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