Synchronous logic synthesis: algorithms for cycle-time minimization

A novel approach to logic synthesis of digital synchronous circuits is presented. A model for synchronous circuits that supports logic transformations aimed at optimizing the circuit performance is presented. Previous synthesis approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. Experimental results on benchmark circuits are reported