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A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing

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S. S. SapatnekarAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 19, Issue 5

Pages 550 - 559

https://doi.org/10.1109/43.845079

Published: 01 November 2006 Publication History

Abstract

Crosstalk is generally recognized as a major problem in integrated circuit design. This paper presents a novel approach to the efficient measurement of the effect of crosstalk on the delay of a net using an algorithm whose worst case complexity is polynomial-time in the number of nets. The cost of the algorithm is seen to be O(n log n) in practice, where n is the number of nets, and it is amenable to being incorporated into the inner loop of a timing optimizer. To illustrate this, the method is applied to reduce the effects of crosstalk in channel routing, where it is seen to give an average improvement of 23% in the delay in a channel as compared to the worst case, as measured by SPICE

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Li YChang YCheng W(2011)A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignmentACM Transactions on Design Automation of Electronic Systems10.1145/1929943.192995116:2(1-25)Online publication date: 7-Apr-2011
https://dl.acm.org/doi/10.1145/1929943.1929951
Das DShebaita AZhou HIsmail YKillpack K(2011)FA-STACIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203532319:3(443-456)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2035323
Das DKillpack KKashyap CJas AZhou H(2010)Pessimism reduction in coupling-aware static timing analysis using timing and logic filteringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203553229:3(466-478)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2035532
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 19, Issue 5

November 2006

130 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Li YChang YCheng W(2011)A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignmentACM Transactions on Design Automation of Electronic Systems10.1145/1929943.192995116:2(1-25)Online publication date: 7-Apr-2011
https://dl.acm.org/doi/10.1145/1929943.1929951
Das DShebaita AZhou HIsmail YKillpack K(2011)FA-STACIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203532319:3(443-456)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2035323
Das DKillpack KKashyap CJas AZhou H(2010)Pessimism reduction in coupling-aware static timing analysis using timing and logic filteringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203553229:3(466-478)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2035532
Gandikota RChopra KBlaauw DSylvester D(2010)Victim alignment in crosstalk-aware timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203548429:2(261-274)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2035484
Gandikota RDing LTehrani PBlaauw D(2009)Worst-case aggressor-victim alignment with current-source driver modelsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629919(13-18)Online publication date: 26-Jul-2009
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Muchherla KChen PMa DWang J(2008)A noniterative equivalent waveform model for timing analysis in presence of crosstalkACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442113:2(1-21)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344421
Chanodia IVelenis D(2008)Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networksAnalog Integrated Circuits and Signal Processing10.1007/s10470-007-9078-056:1-2(13-21)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1007/s10470-007-9078-0
Gandikota RChopra KBlaauw DSylvester DBecer MGeada JGielen G(2007)Victim alignment in crosstalk aware timing analysisProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326220(698-704)Online publication date: 5-Nov-2007
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Gandikota RChopra KBlaauw DSylvester DBecer MLevitan S(2007)Top-k aggressors sets in delay noise analysisProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278523(174-179)Online publication date: 4-Jun-2007
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Tayade RKalyanam VNassif SOrshansky MAbraham JZhou HMacii EYan ZMassoud Y(2007)Estimating path delay distribution considering coupling noiseProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228804(61-66)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228804
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Utilizing reverse short-channel effect for optimal subthreshold circuit design

Utilizing reverse short channel effect for optimal subthreshold circuit design

Crosstalk Aware Static Timing Analysis: A Two Step Approach

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