research-article

Multithreaded processor architectures

Authors:

Gregory T. Byrd,

Mark A. HollidayAuthors Info & Claims

IEEE Spectrum, Volume 32, Issue 8

Pages 38 - 46

https://doi.org/10.1109/6.402166

Published: 01 August 1995 Publication History

Abstract

The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed

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Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130553(722-731)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130553
Li ATay YKumar ACorporaal HKielmann THildebrand DTaufer M(2015)TransitProceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing10.1145/2749246.2749265(101-106)Online publication date: 15-Jun-2015
https://dl.acm.org/doi/10.1145/2749246.2749265
Zuberek WDunkin AIngalls R(2009)Performance limitations of block-multithreaded distributed-memory systemsWinter Simulation Conference10.5555/1995456.1995586(899-907)Online publication date: 13-Dec-2009
https://dl.acm.org/doi/10.5555/1995456.1995586
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Multithreaded processor architectures

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Published: 01 August 1995

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Hamdioui SKvatinsky SCauwenberghs GXie LWald NJoshi SElsayed HCorporaal HBertels K(2017)Memristor for computingProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130553(722-731)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130553
Li ATay YKumar ACorporaal HKielmann THildebrand DTaufer M(2015)TransitProceedings of the 24th International Symposium on High-Performance Parallel and Distributed Computing10.1145/2749246.2749265(101-106)Online publication date: 15-Jun-2015
https://dl.acm.org/doi/10.1145/2749246.2749265
Zuberek WDunkin AIngalls R(2009)Performance limitations of block-multithreaded distributed-memory systemsWinter Simulation Conference10.5555/1995456.1995586(899-907)Online publication date: 13-Dec-2009
https://dl.acm.org/doi/10.5555/1995456.1995586
Yardimci EFranz M(2009)Mostly static program partitioning of binary executablesACM Transactions on Programming Languages and Systems10.1145/1538917.153891831:5(1-46)Online publication date: 3-Jul-2009
https://dl.acm.org/doi/10.1145/1538917.1538918
Zhou XPetrov P(2009)Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systemsACM Transactions on Embedded Computing Systems10.1145/1457255.14572618:2(1-28)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457261
Leadbitter PPage DSmart N(2007)Nondeterministic MultithreadingIEEE Transactions on Computers10.1109/TC.2007.104956:7(992-998)Online publication date: 1-Jul-2007
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Zhou XPetrov PSentovich E(2006)Rapid and low-cost context-switch through embedded processor customization for real-time and control applicationsProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147001(352-357)Online publication date: 24-Jul-2006
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Zuberek W(2002)Analysis of performance bottlenecks in multithreaded multiprocessor systemsFundamenta Informaticae10.5555/634859.63486550:2(223-241)Online publication date: 28-Feb-2002
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Zuberek W(2002)Analysis of Performance Bottlenecks in Multithreaded Multiprocessor SystemsFundamenta Informaticae10.5555/2371069.237107650:2(223-241)Online publication date: 1-Apr-2002
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Sohn ASato MYoo NGaudiot J(1996)Effects of Multithreading on Data and Workload Distribution for Distributed-Memory MultiprocessorsProceedings of the 10th International Parallel Processing Symposium10.5555/645606.661032(116-122)Online publication date: 15-Apr-1996
https://dl.acm.org/doi/10.5555/645606.661032
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Abstract

Cited By

Index Terms

Recommendations

The dynamic simultaneous multithreaded processor

Reducing misspeculation penalty in trace-level speculative multithreaded architectures

Responsive Multithreaded Processor for Distributed Real-Time Processing

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