research-article

Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps

Authors:

J. L. BaerAuthors Info & Claims

IEEE Transactions on Parallel and Distributed Systems, Volume 3, Issue 1

Pages 25 - 44

https://doi.org/10.1109/71.113080

Published: 01 January 1992 Publication History

Abstract

A timestamp-based software-assisted cache coherence scheme that does not require any global communication to enforce the coherence of multiple private caches is proposed. It is intended for shared memory multiprocessors. The scheme is based on a compile-time marking of references and a hardware-based local incoherence detection scheme. The possible incoherence of a cache entry is detected and the associated entryis implicitly invalidated by comparing a clock (related to program flow) and a timestamp (related to the time of update in the cache). Results of a performance comparison, which is based on a trace-driven simulation using actual traces. between the proposed timestamp-based scheme and other software-assisted schemes indicate that the proposed scheme performs significantly better than previous software-assisted schemes, especially when the processors are carefully scheduled so as to maximize the reuse of cache contents. This scheme requires neither a shared resource nor global communication and is, therefore, scalable up to a large number of processors.

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Index Terms

Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Parallel and Distributed Systems

IEEE Transactions on Parallel and Distributed Systems Volume 3, Issue 1

January 1992

125 pages

ISSN:1045-9219

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Copyright © Copyright © 1992 IEEE. All Rights Reserved.

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IEEE Press

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Published: 01 January 1992

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Cited By

Willis BShrivastava AMack JDave SChakrabarti CBrunhaver J(2024)Cyclebite: Extracting Task Graphs From Unstructured Compute-ProgramsIEEE Transactions on Computers10.1109/TC.2023.332750473:1(221-234)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TC.2023.3327504
Zuckerman JGiri DKwon JMantovani PCarloni L(2021)Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480065(350-365)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480065
Young VJaleel ABolotin EEbrahimi ENellans DVilla OOskin MInoue K(2018)Combining HW/SW mechanisms to improve NUMA performance of multi-GPU systemsProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00035(339-351)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00035
Yao YChen WMitra TXiang Y(2017)TC-Release++: An Efficient Timestamp-Based Coherence Protocol for Many-Core ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.271967928:11(3313-3327)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1109/TPDS.2017.2719679
Yao YWang GGe ZMitra TChen WZhang N(2016)Efficient Timestamp-Based Cache Coherence Protocol for Many-Core ArchitecturesProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926270(1-13)Online publication date: 1-Jun-2016
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Sung HAdve S(2015)DeNovoSyncACM SIGARCH Computer Architecture News10.1145/2786763.269435643:1(545-559)Online publication date: 14-Mar-2015
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Sung HAdve SOzturk OEbcioglu KDwarkadas S(2015)DeNovoSyncProceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/2694344.2694356(545-559)Online publication date: 14-Mar-2015
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