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A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures

Published: 01 February 1993 Publication History
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  • Abstract

    The authors present a compile-time scheduling heuristic called dynamic level scheduling,which accounts for interprocessor communication overhead when mappingprecedence-constrained, communicating tasks onto heterogeneous processorarchitectures with limited or possibly irregular interconnection structures. This techniqueuses dynamically-changing priorities to match tasks with processors at each step, andschedules over both spatial and temporal dimensions to eliminate shared resourcecontention. This method is fast, flexible, widely targetable, and displays promisingperformance.

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    Published In

    cover image IEEE Transactions on Parallel and Distributed Systems
    IEEE Transactions on Parallel and Distributed Systems  Volume 4, Issue 2
    February 1993
    120 pages

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    IEEE Press

    Publication History

    Published: 01 February 1993

    Author Tags

    1. Index Termsspatial dimensions
    2. communicating tasks
    3. compile-time scheduling heuristic
    4. dynamic level scheduling
    5. interconnection-constrainedheterogeneous processor architectures
    6. parallel architectures
    7. scheduling
    8. temporal dimensions

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