Article

Latency Sensitive FMA Design

Authors:

Sameh Galal,

Mark HorowitzAuthors Info & Claims

ARITH '11: Proceedings of the 2011 IEEE 20th Symposium on Computer Arithmetic

Pages 129 - 138

https://doi.org/10.1109/ARITH.2011.26

Published: 25 July 2011 Publication History

Abstract

The implementation of merged floating-point multiply-add operations can be optimized in many ways. For latency sensitive applications, our cascade design reduces the accumulation dependent latency by 2x over a fused design, at a cost of a 13% increase in non-accumulation dependent latency. A simple in-order execution model shows this design is superior in most applications, providing 12% average reduction in FP stalls, and improves performance by up to 6%. Simulations of superscalar out-of-order machines show 4% average improvement in CPI in 2-way machines and 4.6% in 4-way machines. The cascade design has the same area and energy budget as a traditional fused multiple-add FMA.

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Gopireddy BSkarlatos DZhu WTorrellas J(2018)HetCoreProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00072(802-815)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00072
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGARCH Computer Architecture News10.1145/2654822.254197842:1(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541978
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGPLAN Notices10.1145/2644865.254197849:4(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2644865.2541978
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Published In

ARITH '11: Proceedings of the 2011 IEEE 20th Symposium on Computer Arithmetic

July 2011

226 pages

ISBN:9780769543185

Publisher

IEEE Computer Society

United States

Publication History

Published: 25 July 2011

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Fused Multiply Add

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Gopireddy BSkarlatos DZhu WTorrellas J(2018)HetCoreProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00072(802-815)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00072
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGARCH Computer Architecture News10.1145/2654822.254197842:1(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2654822.2541978
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel D(2014)Speculative hardware/software co-designed floating-point multiply-add fusionACM SIGPLAN Notices10.1145/2644865.254197849:4(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2644865.2541978
Lupon MGibert EMagklis GSamudrala SMartínez RStavrou KDitzel DBalasubramonian RDavis AAdve S(2014)Speculative hardware/software co-designed floating-point multiply-add fusionProceedings of the 19th international conference on Architectural support for programming languages and operating systems10.1145/2541940.2541978(623-638)Online publication date: 24-Feb-2014
https://dl.acm.org/doi/10.1145/2541940.2541978

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Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support

An Efficient Hardware-Based Higher Radix Floating Point MAC Design

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