Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction

Statistical timing characterization for standard cell library poses significant challenge to accuracy and runtime cost. Prior analytical and machine learning-based methods neglect the profound influence induced by layout-dependent parasitic resistor and capacitor (RC) network in cell netlist as well as the timing correlation between topological structures of cells and process, voltage, and temperature (PVT) corners, resulting in tremendous simulation effort and/or poor accuracy. In this work, an accurate and efficient statistical cell timing library characterization framework is proposed based on heterogeneous graph attention network (HGAT) assisted with parasitic RC reduction approach, where the transistors and parasitic RC in cell are represented as heterogeneous nodes for graph learning and redundant RC nodes are removed to alleviate node imbalance issue and improve prediction accuracy. The proposed framework was validated with TSMC 22nm standard cells under multiple PVT corners to predict the standard deviation of cell delay with the error of 2.67% on average for all validated cells in terms of relative Root Mean Squared Error (rRMSE) with 3 x characterization runtime speedup, achieving 2.7~6.9x accuracy improvement compared with prior works. The predicted statistical timing libraries were further validated with ISCAS'89 benchmark circuits for statistical static timing analysis (SSTA), where the critical path delay at 3σ percentile point is reported with the average mismatch of 1.34ps compared with foundry-provided library, showing 10.7~14.5x better accuracy than the competitive approaches.