research-article

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration

Authors:

Xiaowei LiAuthors Info & Claims

ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation Conference

Pages 58 - 64

https://doi.org/10.1109/ASP-DAC58780.2024.10473888

Published: 03 April 2024 Publication History

Abstract

The stagnation of Moore's law stimulates the concept of breaking monolithic chips into smaller chiplets. However, tactic design partitioning remains an unaddressed issue despite its crucial role in chip product cost reduction. In this paper, we propose Chipletizer, a framework to guide the design partitioning for those who would benefit from chiplet reuse across a line of SoC products. The proposed generic framework supports the repartitioning of multiple SoCs into reusable chiplets economically and efficiently with user-specified parameters. Experimental results show that, compared with existing partitioning strategies, our proposed framework achieves notable cost improvement on realistic products with acceptable power and latency overheads.

References

[1]

S. Naffziger et al., "Pioneering chiplet technology and design for the amd epyc^TM and ryzen^TM processor families: Industrial product," in ISCA, 2021, pp. 57--70.

[2]

M. Khazraee et al., "Moonwalk: Nre optimization in asic clouds," ACM SIGARCH CAN, vol. 45, no. 1, pp. 511--526, 2017.

Digital Library

[3]

D. Stow et al., "Investigation of cost-optimal network-on-chip for passive and active interposer systems," in SLIP, 2019, pp. 1--8.

[4]

B. Vinnakota et al., "The open domain-specific architecture," IEEE Micro, vol. 41, no. 1, pp. 30--36, 2021.

Digital Library

[5]

P. Ehrett et al., "chopin: composing cost-effective custom chips with algorithmic chiplets," in ICCD, 2021, pp. 395--399.

[6]

Y. Feng et al., "Chiplet actuary: A quantitative cost model and multi-chiplet architecture exploration," in DAC, 2022, pp. 121--126.

[7]

S.-J. Chen et al., "Tutorial on vlsi partitioning," VLSI design, vol. 11, no. 3, pp. 175--218, 2000.

[8]

J. Kim et al., "Architecture, chip, and package co-design flow for 2.5 d ic design enabling heterogeneous ip reuse," in DAC, 2019, pp. 1--6.

[9]

S. Bharadwaj et al., "Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling," in DAC, 2020, pp. 1--6.

[10]

N. E. Jerger et al., "Noc architectures for silicon interposer systems," in Micro, 2014, pp. 458--470.

[11]

J. Yin et al., "Modular routing design for chiplet-based systems," in ISCA, 2018, pp. 726--738.

[12]

D. D. Sharma et al., "Universal chiplet interconnect express (ucie)®: An open industry standard for innovations with chiplets at package level," TCPMT, 2022.

[13]

S. Osmolovskyi et al., "Optimal die placement for interposer-based 3d ics," in ASP-DAC, 2018, pp. 513--520.

[14]

A. Coskun et al., "Cross-layer co-optimization of network design and chiplet placement in 2.5-d systems," TCAD, pp. 5183--5196, 2020.

[15]

M. A. Kabir et al., "Chiplet-package co-design for 2.5d systems using standard asic cad tools," in ASP-DAC, 2020, pp. 351--356.

[16]

S. Pal et al., "A case for packageless processors," in HPCA, 2018, pp. 466--479.

[17]

T.-C. Chen et al., "Modern floorplanning based on b/sup ^*/-tree and fast simulated annealing," TCAD, vol. 25, no. 4, pp. 637--650, 2006.

Digital Library

[18]

F. Li et al., "Noception: a fast ppa prediction framework for network-on-chips using graph neural network," in DATE, 2022, pp. 1035--1040.

[19]

J. Xia et al., "Kunpeng 920: The first 7-nm chiplet-based 64-core arm soc for cloud services," IEEE Micro, vol. 41, no. 5, pp. 67--75, 2021.

Digital Library

[20]

I. E. Papazian, "New 3rd gen intel® xeon® scalable processor (codename: Ice lake-sp)." in Hot Chips Symposium, 2020, pp. 1--22.

[21]

"Rockchip products." [Online]. Available: https://www.rock-chips.com

Cited By

Du YWang YLi BLi FLiang SLi HLi XHan YDe V(2024)Chiplever: Towards Effortless Extension of Chiplet-based System for FHEProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657321(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657321

Index Terms

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration
1. Applied computing
  1. Physical sciences and engineering
2. Hardware
  1. Electronic design automation

Index terms have been assigned to the content through auto-classification.

Recommendations

Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Multi-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is a frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the cost superiority of multi-chip integration over monolithic ...
Heterogeneous Die-to-Die Interfaces: Enabling More Flexible Chiplet Interconnection Systems
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture

The chiplet architecture is one of the emerging methodologies and is believed to be scalable and economical. However, most current multi-chiplet systems are based on one uniform die-to-die interface, which severely limits flexibility. First, any ...
Modular routing design for chiplet-based systems
ISCA '18: Proceedings of the 45th Annual International Symposium on Computer Architecture

System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation Conference

January 2024

1008 pages

ISBN:9798350393545

DOI:10.1109/3655039

General Chair:
Taewhan Kim
Seoul National University

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press

Publication History

Published: 03 April 2024

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ASPDAC '24

Sponsor:

SIGDA

ASPDAC '24: 29th Asia and South Pacific Design Automation Conference

January 22 - 25, 2024

Incheon, Republic of Korea

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
98
Total Downloads

Downloads (Last 12 months)98
Downloads (Last 6 weeks)6

Reflects downloads up to 06 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Du YWang YLi BLi FLiang SLi HLi XHan YDe V(2024)Chiplever: Towards Effortless Extension of Chiplet-based System for FHEProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657321(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657321

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten