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Refinement Maps for Efficient Verification of Processor Models

Published: 07 March 2005 Publication History

Abstract

While most of the effort in improving verification times for pipeline machine verification has focused on faster decision procedures, we show that the refinement maps used also have a drastic impact on verification times. We introduce a new class of refinement maps for pipelined machine verification, and using the state-of-the-art verification tools UCLID and Siege we show that one can attain several orders of magnitude improvements in verification times over the standard flushing-based refinement maps, even enabling the verification of machines that are too complex to otherwise automatically verify.

References

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{2} R. E. Bryant, S. German, and M. N. Velev. Exploiting positive equality in a logic of equality with uninterpreted functions. In N. Halbwachs and D. Peled, editors, Computer-Aided Verification-CAV '99, volume 1633 of LNCS, pages 470-482. Springer-Verlag, 1999.
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{3} R. E. Bryant, S. K. Lahiri, and S. Seshia. Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions. In E. Brinksma and K. Larsen, editors, Computer-Aided Verification-CAV 2002, volume 2404 of LNCS, pages 78-92. Springer-Verlag, 2002.
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{4} J. R. Burch and D. L. Dill. Automatic verification of pipelined microprocessor control. In Computer-Aided Verification (CAV '94), volume 818 of LNCS, pages 68-80. Springer-Verlag, 1994.
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{5} R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Proof of correctness of a processor with reorder buffer using the completion functions approach. In N. Halbwachs and D. Peled, editors, Computer-Aided Verification-CAV '99, volume 1633 of LNCS. Springer-Verlag, 1999.
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{6} M. Kaufmann, P. Manolios, and J. S. Moore. Computer-Aided Reasoning: An Approach. Kluwer Academic Publishers, July 2000.
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{7} M. Kaufmann and J. S. Moore. ACL2 homepage. See URL http://www.cs.utexas.edu/users/- moore/acl2.
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{8} S. Lahiri, S. Seshia, and R. Bryant. Modeling and verification of out-of-order microprocessors using UCLID. In Formal Methods in Computer-Aided Design (FMCAD'02), volume 2517 of LNCS, pages 142-159. Springer-Verlag, 2002.
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{9} P. Manolios. Correctness of pipelined machines. In W. A. Hunt, Jr. and S. D. Johnson, editors, Formal Methods in Computer-Aided Design-FMCAD 2000, volume 1954 of LNCS, pages 161-178. Springer-Verlag, 2000.
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{10} P. Manolios. Mechanical Verification of Reactive Systems. PhD thesis, University of Texas at Austin, August 2001. See URL http://www.cc.gatech.edu/~manolios/- publications.html.
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{11} P. Manolios and S. Srinivasan. Automatic verification of safety and liveness for xscale-like processor models using web refinements. In Design, Automation, and Test in Europe , 2004.
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{12} L. Ryan. Siege homepage. See URL http://www.cs.- sfu.ca/~loryan/personal.
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{13} J. Sawada. Formal Verification of an Advanced Pipelined Machine. PhD thesis, University of Texas at Austin, Dec. 1999. See URL http://www.cs.utexas.edu/- users/sawada/dissertation/.
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{14} J. Sawada. Verification of a simple pipelined machine model. In M. Kaufmann, P. Manolios, and J. S. Moore, editors, Computer-Aided Reasoning: ACL2 Case Studies, pages 137- 150. Kluwer Academic Publishers, June 2000.
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{15} S. A. Seshia, S. K. Lahiri, and R. E. Bryant. A hybrid SAT-based decision procedure for separation logic with uninterpreted functions. In Design Automation Conference (DAC 03), pages 425-430, 2003.

Cited By

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  • (2012)Design and analysis of adaptive processorACM Transactions on Reconfigurable Technology and Systems10.1145/2133352.21333575:1(1-34)Online publication date: 23-Mar-2012
  • (2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
  • (2011)Learning conditional abstractionsProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157674(116-124)Online publication date: 30-Oct-2011
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cover image ACM Conferences
DATE '05: Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
March 2005
630 pages
ISBN:0769522882

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IEEE Computer Society

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Published: 07 March 2005

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View all
  • (2012)Design and analysis of adaptive processorACM Transactions on Reconfigurable Technology and Systems10.1145/2133352.21333575:1(1-34)Online publication date: 23-Mar-2012
  • (2011)DesynchronizationProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157687(215-222)Online publication date: 30-Oct-2011
  • (2011)Learning conditional abstractionsProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157674(116-124)Online publication date: 30-Oct-2011
  • (2008)Automatic verification of safety and liveness for pipelined machines using WEB refinementACM Transactions on Design Automation of Electronic Systems10.1145/1367045.136705413:3(1-19)Online publication date: 25-Jul-2008
  • (2007)A Survey of Hybrid Techniques for Functional VerificationIEEE Design & Test10.1109/MDT.2007.3024:2(112-122)Online publication date: 1-Mar-2007
  • (2006)Monolithic verification of deep pipelines with collapsed flushingProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131825(1234-1239)Online publication date: 6-Mar-2006
  • (2006)Solving SAT and SAT Modulo TheoriesJournal of the ACM10.1145/1217856.121785953:6(937-977)Online publication date: 1-Nov-2006
  • (2006)Refinement and theorem provingProceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems10.1007/11757283_7(176-210)Online publication date: 22-May-2006
  • (2005)A complete compositional reasoning framework for the efficient verification of pipelined machinesProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129723(863-870)Online publication date: 31-May-2005

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