Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1109/IPDPS.2005.416guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks

Published: 04 April 2005 Publication History

Abstract

Predictive multiplexed switching is a new approach for building interconnection switches for high performance parallel systems. This approach advocates sacrificing some link bandwidth in return for more efficient network control and simpler connection management. The main idea is to depart from the traditional packet and wormhole switching in favor of row data communication over established communication pipes (connections). The overhead of this circuit switching approach can be justified when established connections are repeatedly used before they are torn down. For this, we use multiplexing to allow multiple connections to share the same resources (links and switches), thus avoiding tearing down connections prematurely. The connection establishment overhead is further reduced by exploring communication locality and predictability in applications that exhibit these properties. We present the design of an interconnection system which is based on multiplexed switching and which establishes connections either reactively, in response to dynamically generated requests, or proactively, in response to compiler or application directives. A communication prediction component may be supported to reduce the network control overhead in applications that exhibit communication locality and predictability. The design is evaluated using hardware design, synthesis, and cycle-accurate simulation. Comparison with more traditional switching paradigms shows the potential of our predictive multiplexed switching approach.

References

[1]
J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks An Engineering Approach. Morgan Kaufmann, 2003. Revised Printing.
[2]
C. Salisbury and R. Melhem, "A high speed scheduler/ controller for unbuffered Banyan networks," Computer Communications Journal, vol. 24, no. 9, pp. 1158-1169, 2001.
[3]
J. Kim and D. J. Lilja, "Characterization of communication patterns in message-passing parallel scientific application program," in Proc. of the Second International Workshop on Network-Based Parallel Computing: Communication, Architecture, and Applications (G. Goos, J. Hartmanis, and J. Leeuwen, eds.), pp. 202-216, 1998.
[4]
A. Afsahi, Design and Evaluation of Communication Latency Hiding/Reduction Techniques for Message-Passing Enviroments. PhD thesis, University of Victoria, Canada, 2000.
[5]
W. Ho and T. Pinkston, "A methodology for designing efficient on-chip interconnects on well-behaved communication patterns," in Proc. of the 9th Int. Symposium on High-Performance Computer Architecture, pp. 377-388, 2003.
[6]
H. G. Dietz and T. Mattox, "Compiler techniques for Flat Neighborhood Networks," in Proc. of 13th Int. Workshop on Languages and Compilers for Parallel Computing, 2000.
[7]
K. L. Johnson, "The impact of commucation locality on large-scale multiprocessor performance," in Proc. of the 19th Annual International Symposium on Computer Architecture, 1992.
[8]
L. Roh and W. A. Najjar, "Analysis of communications and overhead reduction in multithreaded execution," in Proc. of the Int. Conf. on Parallel Architectures and Compilation Techniques, 1995.
[9]
J. Fernandez and E. Frachtenberg, "BCS-MPI: a new approach in the system software design for large-scale parallel computers," in Proc. of the ACM/IEEE Conf. on Supercomputing, 2003.
[10]
R. Melhem, "Time-multiplexing optical interconnection networks; why does it pay off?," in Proc. of the ICPP Workshop on Challenges for Parallel Processing, 1995.
[11]
X. Yuan, R. Melhem, and R. Gupta, "Algorithms for supporting compiled communication," IEEE Trans. on Parallel and Distributed Systems, vol. 14, no. 2, pp. 107-118, 2003.
[12]
J. Liang, S. Swaminathan, and R. Tessier, "aSOC: a scalable, single-chip communications architecture," in Proc. of the IEEE Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 37-46, Oct. 2000.
[13]
A. Faraj and X. Yuan, "Communication characteristics in the NAS parallel benchmarks," in Proc. 14th IASTED Int. Conf. on Parallel and Distributed Computing and Systems, IPDCS 2002, (Cambridge, MA), pp. 729-734, November 2002.
[14]
D. Lahaut and C. Germain, "Static communications in parallel scientific programs," in Proc. of PARLE, 1994.
[15]
W. Thies, M. Karczmarek, and S. Amarsinghe, "StreamIt: a language for streaming applications," in Proc. of the Int. Conf. on Compiler Construction, 2002.
[16]
S. Hinrichs, Compiler directed architecture-dependent communication optimization. PhD thesis, Carnegie Mellon University, 1995.
[17]
T. Gross, "Communication in iWarp systems," in Proc. of Supercomputing, 1989.
[18]
T. Gross, A. Hasegawa, S. Hinrichs, D. O'Hallaron, and T. Stricker, "Communication styles for parallel systems," IEEE Computer, 1994.
[19]
F. Cappello and C. Germain, "Toward high communication performance through compiled communications on a circuit switched interconnection network," in Proc. of the First IEEE Symposium on High-Performance Computer Architecture, 1995.
[20]
G. Viswanathan and J. Larus, "Compiler-directed shared-memory communication for iterative parallel applications," in Proc. of the 1996 ACM/IEEE Conf. on Supercomputing, 1996.
[21]
M. F. Sakr, S. P. Levitan, D. M. Chiarulli, B. G. Horne, and C. L. Giles, "Predicting multiprocessor memory access patterns with learning models," in Proc. of 14th Int. Conf. on Machine Learning, pp. 305-312, 1997.
[22]
S. Kaxiras and C. Young, "Coherence communication prediction in shared-memory multiprocessors," in Proc. of the 16th Int. High Performance Computer Architecture, 2000.
[23]
National Semiconductor Co., "DS90CP04 4×4 low power 2.5 Gb/s LVDS digital cross-point switch." Data Sheet, Jan. 2004.
[24]
C. Qiao and R. Melhem, "Dynamic reconfiguration of optically interconnected networks with time division multiplexing," the Journal of Parallel and Distributed Computing, vol. 22, no. 2, pp. 268-278, 1994.

Cited By

View all
  • (2009)FACTProceedings of the Conference on High Performance Computing Networking, Storage and Analysis10.1145/1654059.1654087(1-12)Online publication date: 14-Nov-2009
  • (2008)Circuit-Switched CoherenceProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397999(193-202)Online publication date: 7-Apr-2008
  • (2008)Packet prediction for speculative cut-through switchingProceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1477942.1477957(99-108)Online publication date: 6-Nov-2008
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings
IPDPS '05: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
April 2005
ISBN:0769523129

Publisher

IEEE Computer Society

United States

Publication History

Published: 04 April 2005

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 26 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2009)FACTProceedings of the Conference on High Performance Computing Networking, Storage and Analysis10.1145/1654059.1654087(1-12)Online publication date: 14-Nov-2009
  • (2008)Circuit-Switched CoherenceProceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip10.5555/1397757.1397999(193-202)Online publication date: 7-Apr-2008
  • (2008)Packet prediction for speculative cut-through switchingProceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems10.1145/1477942.1477957(99-108)Online publication date: 6-Nov-2008
  • (2007)Low Diameter Interconnections for Routing in High-Performance Parallel SystemsIEEE Transactions on Computers10.1109/TC.2007.100456:4(502-510)Online publication date: 1-Apr-2007
  • (2006)A compiler-based communication analysis approach for multiprocessor systemsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899019(85-85)Online publication date: 25-Apr-2006
  • (2006)A near-optimal real-time hardware scheduler for large cardinality crossbar switchesProceedings of the 2006 ACM/IEEE conference on Supercomputing10.1145/1188455.1188554(94-es)Online publication date: 11-Nov-2006

View Options

View options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media