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Evolution of the samsung exynos CPU microarchitecture

Published: 23 September 2020 Publication History

Abstract

The Samsung Exynos family of cores are high-performance "big" processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.

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Cited By

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  • (2024)Tyche: An Efficient and General Prefetcher for Indirect Memory AccessesACM Transactions on Architecture and Code Optimization10.1145/3641853Online publication date: 22-Jan-2024
  • (2023)Protean: Resource-efficient Instruction PrefetchingProceedings of the International Symposium on Memory Systems10.1145/3631882.3631904(1-13)Online publication date: 2-Oct-2023
  • (2023)Branch Target Buffer OrganizationsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623774(240-253)Online publication date: 28-Oct-2023
  • Show More Cited By

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cover image ACM Conferences
ISCA '20: Proceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture
May 2020
1152 pages
ISBN:9781728146614

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Published: 23 September 2020

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Author Tags

  1. branch prediction
  2. microprocessor
  3. prefetching
  4. superscalar

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ISCA '20
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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

View all
  • (2024)Tyche: An Efficient and General Prefetcher for Indirect Memory AccessesACM Transactions on Architecture and Code Optimization10.1145/3641853Online publication date: 22-Jan-2024
  • (2023)Protean: Resource-efficient Instruction PrefetchingProceedings of the International Symposium on Memory Systems10.1145/3631882.3631904(1-13)Online publication date: 2-Oct-2023
  • (2023)Branch Target Buffer OrganizationsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623774(240-253)Online publication date: 28-Oct-2023
  • (2023)Warming Up a Cold Front-End with IgniteProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614258(254-267)Online publication date: 28-Oct-2023
  • (2023)EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction CachingProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589097(1-13)Online publication date: 17-Jun-2023
  • (2021)Twig: Profile-Guided BTB Prefetching for Data Center ApplicationsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480124(816-829)Online publication date: 18-Oct-2021
  • (2021)Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480050(792-803)Online publication date: 18-Oct-2021
  • (2021)RippleProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00063(734-747)Online publication date: 14-Jun-2021
  • (2021)A cost-effective entangling prefetcher for instructionsProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00017(99-111)Online publication date: 14-Jun-2021

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