A Methodology and Toolset to Enable SystemC and VHDL Co-simulation

The new design challenges imposed by the increasing difficulties of today's electronic systems obligated design- ers to develop new methodologies. System-level design and Platform-based design are playing an important rule in the electronics industry, and design reuse is a key concept. Sys- temC is a design language which is being largely adopted to raise the abstraction level of hardware design and verifica- tion, becoming an important system design language nowa- days. Considering the large amount of VHDL RTL mod- ules already available and that systems design are hardly ever started from scratch, co-simulating VHDL and Sys- temC hardware modules becomes very desirable. This pa- per presents a new methodology, based on an open-source toolset (libraries and programs), to co-simulate SystemC and VHDL components. We use a platform case study to measure simulation performance and compare our infras- tructure to Modelsim.