Context-aware Post Routing Redundant Via Insertion
Abstract
Recommendations
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by ...
Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate
Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is a typical approach for improving yield and reliability. Cell-based design methodologies are ...
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration
Yield loss caused by via failures is unacceptably high in many semiconductor manufacturing processes. Redundant via insertion (RVI) is a typical approach for improving manufacturing competitiveness. The double-via insertion in concurrent routing or post-...
Comments
Information & Contributors
Information
Published In
Publisher
IEEE Computer Society
United States
Publication History
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0