Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1109/ISVLSI.2009.39guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Context-aware Post Routing Redundant Via Insertion

Published: 13 May 2009 Publication History

Abstract

Effective algorithms have been invented for post-routing redundant via insertion (RVI). However, implementations of these algorithms often ignore some practical issues. In this article, we implement a post-routing RVI algorithm that takes into account interconnect contexts during RVI. Experimental results show that our context-aware RVI on average raises via1 (vias between metal layer 1 and 2) insertion rate from 37.4% to 72.1% and total insertion rate from 72.5% to 85.8%. On average, it increases RVI rate of critical paths by 3.6%. Besides, with redundant pin-area minimization, our approach reduces metal 1 and metal 2 area used for RVI at pins by 3%.

Recommendations

Comments

Information & Contributors

Information

Published In

cover image Guide Proceedings
ISVLSI '09: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
May 2009
312 pages
ISBN:9780769536842

Publisher

IEEE Computer Society

United States

Publication History

Published: 13 May 2009

Author Tags

  1. Redundant via
  2. VLSI
  3. design for manufacturing
  4. double via

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 0
    Total Downloads
  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 23 Dec 2024

Other Metrics

Citations

View Options

View options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media