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- López SGarnica ÓAlbonesi DDropsho SLanchares JHidalgo J(2011)A phase adaptive cache hierarchy for SMT processorsMicroprocessors & Microsystems10.1016/j.micpro.2011.08.00835:8(683-694)Online publication date: 1-Nov-2011
- Colmenar JGarnica OLanchares JHidalgo J(2010)Simulating a LAGS processor to consider variable latency on L1 D-CacheProceedings of the 2010 Summer Computer Simulation Conference10.5555/1999416.1999421(56-63)Online publication date: 11-Jul-2010
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