research-article

IBM Power5 Chip: A Dual-Core Multithreaded Processor

Authors:

Ron Kalla,

Balaram Sinharoy,

Joel M. TendlerAuthors Info & Claims

IEEE Micro, Volume 24, Issue 2

Pages 40 - 47

https://doi.org/10.1109/MM.2004.1289290

Published: 01 March 2004 Publication History

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Abstract

Featuring single- and multithreaded execution, the Power5 provides higher performance in the single-threaded mode than its Power4 predecessor at equivalent frequencies. Enhancements include dynamic resource balancing to efficiently allocate system resources to each thread, software-controlled thread prioritization, and dynamic power management to reduce power consumption without affecting performance.

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Eyerman SHeirman WVan Den Steen SHur I(2021)Enabling Branch-Mispredict Level Parallelism by Selectively Flushing InstructionsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480045(767-778)Online publication date: 18-Oct-2021
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IBM Power5 Chip: A Dual-Core Multithreaded Processor

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Published In

IEEE Micro Volume 24, Issue 2

March 2004

134 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 March 2004

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Eyerman SHeirman WVan Den Steen SHur I(2021)Enabling Branch-Mispredict Level Parallelism by Selectively Flushing InstructionsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480045(767-778)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480045
Hassan MPatel HPellizzoni R(2017)PMCACM Transactions on Embedded Computing Systems10.1145/301961116:4(1-28)Online publication date: 11-May-2017
https://dl.acm.org/doi/10.1145/3019611
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Sinharoy BVan Norstrand JEickemeyer RLe HLeenstra JNguyen DKonigsburg BWard KBrown MMoreira JLevitan DTung SHrusecky DBishop JGschwind MBoersma MKroener MKaltenbach MKarkhanis TFernsler K(2015)IBM POWER8 processor core microarchitectureIBM Journal of Research and Development10.1147/JRD.2014.237611259:1(2:1-2:21)Online publication date: 1-Jan-2015
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