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FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery

Published: 12 September 2009 Publication History

Abstract

Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current HTM systems use either eager or lazy version management. Eager systems that keep new values in-place while they hold old values in a software log, suffer long delays when aborts are frequent because the pre-transactional state is recovered by software. Lazy systems that buffer new values in specialized hardware offer complex and inefficient solutions to handle hardware overflows, which are common in applications with coarse-grain transactions.In this paper, we present FASTM, an eager log-based HTM that takes advantage of the processor’s cache hierarchy to provide fast abort recovery. FASTM uses a novel coherence protocol to buffer the transactional modifications in the first level cache and to keep the non-speculative values in the higher levels of the memory hierarchy. This mechanism allows fast abort recovery of transactions that do not overflow the first level cache resources.Contrary to lazy HTM systems, committing transactions do not have to perform any actions in order to make their results visible to the rest of the system. FASTM keeps the pre-transactional state in a software-managed log as well, which permits the eviction of speculative values and enables transparent execution even in the case of cache overflow. This approach simplifies eviction policies without degrading performance, because it only falls back to a software abort recovery for transactions whose modified state has overflowed the cache.Simulation results show that FASTM achieves a speed-up of 43% compared to LogTM-SE, improving the scalability of applications with coarse-grain transactions and obtaining similar performance to an ideal eager HTM with zero-cost abort recovery.

Cited By

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  • (2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
  • (2018)Improving Parallelism in Hardware Transactional MemoryACM Transactions on Architecture and Code Optimization10.1145/317796215:1(1-24)Online publication date: 22-Mar-2018
  • (2018)NVHTJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.013120:C(339-354)Online publication date: 1-Oct-2018
  • Show More Cited By

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Published In

cover image Guide Proceedings
PACT '09: Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
September 2009
364 pages
ISBN:9780769537719

Publisher

IEEE Computer Society

United States

Publication History

Published: 12 September 2009

Author Tags

  1. FASTM
  2. fast abort recovery
  3. harwdare transactional memory
  4. transactional coherence protocols

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Overall Acceptance Rate 121 of 471 submissions, 26%

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Cited By

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  • (2018)Transactional pre-abort handlers in hardware transactional memoryProceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques10.1145/3243176.3243186(1-11)Online publication date: 1-Nov-2018
  • (2018)Improving Parallelism in Hardware Transactional MemoryACM Transactions on Architecture and Code Optimization10.1145/317796215:1(1-24)Online publication date: 22-Mar-2018
  • (2018)NVHTJournal of Parallel and Distributed Computing10.1016/j.jpdc.2018.02.013120:C(339-354)Online publication date: 1-Oct-2018
  • (2017)FPGA-Accelerated Transactional Execution of Graph WorkloadsProceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3020078.3021743(227-236)Online publication date: 22-Feb-2017
  • (2017)Restart Optimization for Transactional Memory with Lazy Conflict DetectionInternational Journal of Parallel Programming10.1007/s10766-016-0411-z45:3(482-507)Online publication date: 1-Jun-2017
  • (2016)A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction ExecutionACM Transactions on Architecture and Code Optimization10.1145/283702812:4(1-26)Online publication date: 4-Jan-2016
  • (2014)Consolidated conflict detection for hardware transactional memoryProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628076(201-212)Online publication date: 24-Aug-2014
  • (2014)Efficient execution of speculative threads and transactions with hardware transactional memoryFuture Generation Computer Systems10.1016/j.future.2013.06.01730:C(242-253)Online publication date: 1-Jan-2014
  • (2013)SCIN-cacheACM Transactions on Architecture and Code Optimization10.1145/2400682.24007179:4(1-26)Online publication date: 20-Jan-2013
  • (2013)An integrated pseudo-associativity and relaxed-order approach to hardware transactional memoryACM Transactions on Architecture and Code Optimization10.1145/2400682.24007019:4(1-26)Online publication date: 20-Jan-2013
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