research-article

Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic

Authors:

M. J. Y. Williams,

J. B. AngellAuthors Info & Claims

IEEE Transactions on Computers, Volume 22, Issue 1

Pages 46 - 60

https://doi.org/10.1109/T-C.1973.223600

Published: 01 January 1973 Publication History

Abstract

With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture. The problem is particularly acute for sequential circuits, where there are difficulties in setting and checking the state of the system.

References

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Cited By

Schley GDalirsani AEggenberger MHatami NWunderlich HRadetzki M(2017)Multi-Layer Diagnosis for Fault-Tolerant Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2016.262805866:5(848-861)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2628058
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Wunderlich HRadetzki MIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Multi-Layer Test and Diagnosis for Dependable NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788708(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2788708
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Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 22, Issue 1

January 1973

117 pages

ISSN:0018-9340

Issue’s Table of Contents

Copyright © 1973.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 January 1973

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Cited By

Schley GDalirsani AEggenberger MHatami NWunderlich HRadetzki M(2017)Multi-Layer Diagnosis for Fault-Tolerant Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2016.262805866:5(848-861)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2628058
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Wunderlich HRadetzki MIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Multi-Layer Test and Diagnosis for Dependable NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2788708(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2788708
Zhu CWeissenbacher GMalik SChang Y(2014)Silicon fault diagnosis using sequence interpolation with backbonesProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691434(348-355)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691434
Imhof MWunderlich HFettweis GNebel W(2014)Bit-flipping scan - a unified architecture for fault tolerance and offline testProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616843(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616843
Sarrazin SEvain Sde Barros Naviner LBonhomme YGherman VMacii E(2013)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detectionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485550(1077-1082)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485550
Lin DHong TLi YFallah FGardner DHakim NMitra SMacii E(2013)Overcoming post-silicon validation challenges through quick error detection (QED)Proceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485367(320-325)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485367
Sengupta Dde Paula FHu AVeneris AIvanov ABrunvard EStevens KCavallaro JZhang T(2012)Lazy suspect-set computationProceedings of the great lakes symposium on VLSI10.1145/2206781.2206827(189-194)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206827
De Paula FHu ANahir A(2012)nuTAB-BackSpaceProceedings of the 24th international conference on Computer Aided Verification10.1007/978-3-642-31424-7_37(513-531)Online publication date: 7-Jul-2012
https://dl.acm.org/doi/10.1007/978-3-642-31424-7_37
Zhu CWeissenbacher GMalik SBjesse PSlobodová A(2011)Post-silicon fault localisation using maximum satisfiability and backbonesProceedings of the International Conference on Formal Methods in Computer-Aided Design10.5555/2157654.2157667(63-66)Online publication date: 30-Oct-2011
https://dl.acm.org/doi/10.5555/2157654.2157667
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