research-article

The VLSI Complexity of Sorting

Author:

C. D. ThompsonAuthors Info & Claims

IEEE Transactions on Computers, Volume 32, Issue 12

Pages 1171 - 1184

https://doi.org/10.1109/TC.1983.1676178

Published: 01 December 1983 Publication History

Abstract

The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power. Other adjustments to the model make it possible to compare pipelined and nonpipelined designs.

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Cited By

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Chen RPrasanna V(2017)Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.270512828:11(3100-3113)Online publication date: 6-Oct-2017
https://dl.acm.org/doi/10.1109/TPDS.2017.2705128
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The VLSI Complexity of Sorting
1. Hardware
2. Theory of computation

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 32, Issue 12

December 1983

150 pages

ISSN:0018-9340

Issue’s Table of Contents

Copyright © 1983.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1983

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Cited By

Preethi PMohan KKumar K. SMahapatra K(2022)Sorter Design with Structured Low Power TechniquesSN Computer Science10.1007/s42979-022-01546-74:2Online publication date: 27-Dec-2022
https://dl.acm.org/doi/10.1007/s42979-022-01546-7
Liu XChen MWang SSaad WYin C(2020)Trajectory Design for Energy Harvesting UAV Networks: A Foraging Approach2020 IEEE Wireless Communications and Networking Conference (WCNC)10.1109/WCNC45663.2020.9120514(1-6)Online publication date: 25-May-2020
https://dl.acm.org/doi/10.1109/WCNC45663.2020.9120514
Chen RPrasanna V(2017)Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.270512828:11(3100-3113)Online publication date: 6-Oct-2017
https://dl.acm.org/doi/10.1109/TPDS.2017.2705128
Chen RSiriyal SPrasanna VConstantinides GChen D(2015)Energy and Memory Efficient Mapping of Bitonic Sorting on FPGAProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689068(240-249)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689068
Jakoby ALikiewicz MReischuk RSchindelhauer C(2009)Improving the average delay of sortingTheoretical Computer Science10.1016/j.tcs.2008.10.028410:11(1030-1041)Online publication date: 10-Mar-2009
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Jakoby ALiśkiewicz MReischuk RSchindelhauer C(2007)Improving the average delay of sortingProceedings of the 4th international conference on Theory and applications of models of computation10.5555/1767854.1767886(330-341)Online publication date: 22-May-2007
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Gruau FLhuillier YReitz PTemam OVassiliadis SGaudiot JPiuri V(2004)BLOB computingProceedings of the 1st conference on Computing frontiers10.1145/977091.977111(125-139)Online publication date: 14-Apr-2004
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Cheng SYasuura H(2003)Arbitrary long digit integer sorter HW/SW co-designProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119884(538-543)Online publication date: 21-Jan-2003
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