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Applications considerations in the system design of highly concurrent multiprocessors

Published: 01 November 1987 Publication History
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  • Abstract

    A five-year series of studies, which ended in 1982 and which was supported in part by NASA and in part by Burroughs Corporation, led to the system design of a very large, very high-speed multiprocessor. This system was intended to solve large scientific problems, especially modeling problems such as those in computational aerodynamics. The performance objective was to sustain execution rates up to one billion floating-point operations per second with problems requiring 40 million words of main memory. The viability of this design depended on an in-depth understanding of the projected applications of the system. An overview of the project objectives and the resulting 128 processor design will be presented showing the local private memories available to each processor, the 64 million word shared memory, the dual-omega interconnection network, and the important programming concepts. During the design of the system, studies were conducted which determined the number of processors (a tradeoff with individual processor speed), the memory organization (program and data, private and shared), and the structure of the networks used to interconnect the processor and memory resources. These studies and the important application-related considerations are presented. Although this system was never constructed and tested, it was extensively simulated and the design was completed to sufficient detail to develop a reasonably accurate parts list and implementation plan.

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    • (1995)Static Barrier MIMDJournal of Parallel and Distributed Computing10.1006/jpdc.1995.103525:2(126-132)Online publication date: 1-Mar-1995
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    Published In

    cover image IEEE Transactions on Computers
    IEEE Transactions on Computers  Volume 36, Issue 11
    Nov. 1987
    136 pages

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 01 November 1987

    Author Tags

    1. Application-oriented design
    2. MIMD
    3. computer architecture
    4. computer system design
    5. data memory system
    6. gigaflop execution rates
    7. instruction memory system
    8. multiprocessor
    9. omega network
    10. parallel processing
    11. shared memory systems

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    • (2004)Scalable barrier synchronisation for large-scale shared-memory multiprocessorsInternational Journal of High Performance Computing and Networking10.1504/IJHPCN.2004.0075631:1-3(33-42)Online publication date: 1-Aug-2004
    • (1995)Distributed Hardwired Barrier Synchronization for Scalable Multiprocessor ClustersIEEE Transactions on Parallel and Distributed Systems10.1109/71.3880406:6(591-605)Online publication date: 1-Jun-1995
    • (1995)Static Barrier MIMDJournal of Parallel and Distributed Computing10.1006/jpdc.1995.103525:2(126-132)Online publication date: 1-Mar-1995
    • (1993)Loop Coalescing and Scheduling for Barrier MIMD ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/71.2435314:9(1060-1064)Online publication date: 1-Sep-1993
    • (1992)Subset barrier synchronization on a private-memory parallel systemProceedings of the fourth annual ACM symposium on Parallel algorithms and architectures10.1145/140901.140923(209-218)Online publication date: 1-Jun-1992
    • (1989)Efficient synchronization primitives for large-scale cache-coherent multiprocessorsProceedings of the third international conference on Architectural support for programming languages and operating systems10.1145/70082.68188(64-75)Online publication date: 1-Apr-1989
    • (1989)Efficient synchronization primitives for large-scale cache-coherent multiprocessorsACM SIGARCH Computer Architecture News10.1145/68182.6818817:2(64-75)Online publication date: 1-Apr-1989
    • (1989)Restricted Fetch and Φ operations for parallel processingProceedings of the 3rd international conference on Supercomputing10.1145/318789.318872(410-416)Online publication date: 1-Jun-1989
    • (1988)The Wisconsin multicube: a new large-scale cache-coherent multiprocessorProceedings of the 15th Annual International Symposium on Computer architecture10.5555/52400.52447(422-431)Online publication date: 1-Jun-1988
    • (1988)The Wisconsin multicube: a new large-scale cache-coherent multiprocessorACM SIGARCH Computer Architecture News10.1145/633625.5244716:2(422-431)Online publication date: 17-May-1988
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