research-article

Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications

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H. De ManAuthors Info & Claims

IEEE Transactions on Computers, Volume 54, Issue 1

Pages 76 - 81

https://doi.org/10.1109/TC.2005.2

Published: 01 January 2005 Publication History

Abstract

Cache misses form a major bottleneck for real-time multimedia applications due to the off-chip accesses to the main memory. This results in both a major access bandwidth overhead (and related power consumption) as well as performance penalties. In this paper, we propose a new technique for organizing data in the main memory for data dominated multimedia applications so as to reduce the majority of the conflict cache misses. The focus of this paper is on the formal and heuristic algorithm we use to steer the data layout decisions and the experimental results obtained using a prototype tool. Experiments on real-life demonstrators illustrate that we are able to reduce up to 82 percent of the conflict misses for applications which are already aggressively transformed at source-level. At the same time, we also reduce the off-chip data accesses by up to 78 percent. In addition, we are able to reduce up to 20 percent more conflict misses compared to existing techniques.

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Cited By

Mbaye MBélanger NSavaria YPierre S(2018)Loop acceleration exploration for ASIP architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.210792320:4(684-696)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2107923
Sharifi MZolfaghari B(2018)YAARCThe Journal of Supercomputing10.1007/s11227-007-0147-z44:1(24-40)Online publication date: 30-Dec-2018
https://dl.acm.org/doi/10.1007/s11227-007-0147-z
Filippopoulos ISharma NCatthoor FKjeldsberg PPanda P(2016)Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD ArchitecturesACM Transactions on Embedded Computing Systems10.1145/289475415:3(1-23)Online publication date: 23-May-2016
https://dl.acm.org/doi/10.1145/2894754
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Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 54, Issue 1

January 2005

97 pages

ISSN:0018-9340

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Copyright © 2005.

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IEEE Computer Society

United States

Publication History

Published: 01 January 2005

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Cited By

Mbaye MBélanger NSavaria YPierre S(2018)Loop acceleration exploration for ASIP architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.210792320:4(684-696)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2107923
Sharifi MZolfaghari B(2018)YAARCThe Journal of Supercomputing10.1007/s11227-007-0147-z44:1(24-40)Online publication date: 30-Dec-2018
https://dl.acm.org/doi/10.1007/s11227-007-0147-z
Filippopoulos ISharma NCatthoor FKjeldsberg PPanda P(2016)Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD ArchitecturesACM Transactions on Embedded Computing Systems10.1145/289475415:3(1-23)Online publication date: 23-May-2016
https://dl.acm.org/doi/10.1145/2894754
Sharma NPanda PCatthoor FRaghavan PAa T(2015)Array Interleaving—An Energy-Efficient Data Layout TransformationACM Transactions on Design Automation of Electronic Systems10.1145/274787520:3(1-26)Online publication date: 24-Jun-2015
https://dl.acm.org/doi/10.1145/2747875
Ding WZhang YLiu JKandemir MPhillips JHu AGraeb H(2011)Optimizing data locality using array tilingProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132359(142-149)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132359
Zhang YDing WKandemir MLiu JJang OGaluzzi CCarro LMoshovos APrvulovic M(2011)A data layout optimization framework for NUCA-based multicoresProceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2155620.2155677(489-500)Online publication date: 3-Dec-2011
https://dl.acm.org/doi/10.1145/2155620.2155677
Zhou XPetrov P(2008)Heterogeneously tagged caches for low-power embedded systems with virtual memory supportACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/1344418.134442813:2(1-24)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344428

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