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Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

Published: 01 April 2010 Publication History
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  • Abstract

    A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence, and two target devices: the nVidia GeForce 7900 GTX GPU and a Xilinx Virtex-4 field programmable gate array (FPGA). Two orders of magnitude speedup, over a general-purpose processor, is observed for each device for arithmetic intensive algorithms. An FPGA is superior, over a GPU, for algorithms requiring large numbers of regular memory accesses, while the GPU is superior for algorithms with variable data reuse. In the presence of data dependence, the implementation of a customized data path in an FPGA exceeds GPU performance by up to eight times. The trends of the analysis to newer and future technologies are analyzed.

    Cited By

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    • (2021)Reinhardt: Real-time Reconfigurable Hardware Architecture for Regular Expression Matching in DPIProceedings of the 37th Annual Computer Security Applications Conference10.1145/3485832.3485878(620-633)Online publication date: 6-Dec-2021
    • (2021)HBM Connect: High-Performance HLS Interconnect for FPGA HBMThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439301(116-126)Online publication date: 17-Feb-2021
    • (2020)FPGA Implementations of SVM Classifiers: A ReviewSN Computer Science10.1007/s42979-020-00128-91:3Online publication date: 23-Apr-2020
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    A. Squassabia

    Faced with a practical number-crunching problem, the modern practitioner must address a dilemma: Will my solution be better if I write custom software suitable for a commodity floating-point graphics processing unit (GPU) powerhouse, or should I wrap custom hardware logic with elegance and finesse around the same algorithm__?__ This is not an easy decision: choose the former and deal with the fast, powerful, inexpensive, but also inflexible GPU hardware's idiosyncratic instruction set; choose the latter if you prefer slower-clocked field-programmable gate array (FPGA) hardware to algorithmic requirements. In this paper, Cope et al. take a parametrized, systematic approach to this dilemma. The classification factors are memory access requirements, arithmetic complexity, and data dependence, with each varying over limited semi-quantitative ranges. Oversimplifying the results, reconfigurable hardware logic shows eclectic adaptability to different problem categories, demonstrating competitive throughput across experimental cases that is bracketed within a relatively small range. On the other hand, commodity GPU throughput varies: it excels where the nature of the problem can exploit hardware architecture and it fails elsewhere. The paper analytically and quantitatively describes what makes commodity GPUs better or worse than FPGAs. The paper focuses excessively on commodity GPU hardware, which is already past its prime, having succumbed to marketplace competition. Nevertheless, this work's solid approach and method, if perhaps not all of the included details, are valid. Online Computing Reviews Service

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    Published In

    cover image IEEE Transactions on Computers
    IEEE Transactions on Computers  Volume 59, Issue 4
    April 2010
    143 pages

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 01 April 2010

    Author Tags

    1. Graphics processors
    2. performance measures
    3. real-time and embedded systems
    4. reconfigurable hardware
    5. signal processing systems
    6. video.

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    Cited By

    View all
    • (2021)Reinhardt: Real-time Reconfigurable Hardware Architecture for Regular Expression Matching in DPIProceedings of the 37th Annual Computer Security Applications Conference10.1145/3485832.3485878(620-633)Online publication date: 6-Dec-2021
    • (2021)HBM Connect: High-Performance HLS Interconnect for FPGA HBMThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439301(116-126)Online publication date: 17-Feb-2021
    • (2020)FPGA Implementations of SVM Classifiers: A ReviewSN Computer Science10.1007/s42979-020-00128-91:3Online publication date: 23-Apr-2020
    • (2019)High Performance Heterogeneous Multicore ArchitecturesProceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control10.1145/3386164.3386166(1-5)Online publication date: 25-Sep-2019
    • (2017)Embedded architecture for noise-adaptive video object detection using parameter-compressed background modelingJournal of Real-Time Image Processing10.1007/s11554-014-0418-x13:2(397-414)Online publication date: 1-Jun-2017
    • (2016)Video Anomaly Detection in Real Time on a Power-Aware Heterogeneous PlatformIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2015.249283826:11(2109-2122)Online publication date: 1-Nov-2016
    • (2016)An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessorJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.06.00368:C(17-37)Online publication date: 1-Aug-2016
    • (2015)Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAsACM Transactions on Embedded Computing Systems10.1145/265620714:2(1-23)Online publication date: 17-Feb-2015
    • (2015)Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose ProcessorsMicroprocessors & Microsystems10.1016/j.micpro.2015.01.00139:2(64-73)Online publication date: 1-Mar-2015
    • (2015)Energy-Constrained Multiplication of Non-square Matrices on FPGA-Based SIMD-MIMD Hybrid Multi-core ProcessorsJournal of Signal Processing Systems10.1007/s11265-013-0867-780:2(209-224)Online publication date: 1-Aug-2015
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