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Refresh Now and Then

Published: 01 December 2014 Publication History

Abstract

DRAM stores information in electric charge. Because DRAM cells lose stored charge over time due to leakage, they have to be “refreshed” in a periodic manner to retain the stored information. This refresh activity is a source of increased energy consumption as the DRAM density grows. It also incurs nontrivial performance loss due to the unavailability of memory arrays during refresh. This paper first presents a comprehensive measurement-based characterization study of the cell-level data retention behavior of modern low-power DRAM chips. About 99.7% of the cells could retain the stored information for longer than 1 s at a high temperature. This average cell retention behavior strongly indicates that we can deeply reduce the energy and performance penalty of DRAM refreshing with proper system support. The second part of this paper, accordingly, develops two practical techniques to reduce the frequency of DRAM refresh operations by excluding a few leaky memory cells from use and by skipping refreshing of unused DRAM regions. We have implemented the proposed techniques completely in the Linux OS for experimentation, and measured performance improvement of up to 17.2% with the refresh operation reduction of 93.8% on smartphone like low-power platforms.

Cited By

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  • (2022)Data ConvectionProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/35080276:1(1-25)Online publication date: 28-Feb-2022
  • (2021)SoftRefresh: Targeted refresh for Energy-efficient DRAM systems via Software and Operating Systems supportProceedings of the International Symposium on Memory Systems10.1145/3488423.3519323(1-6)Online publication date: 27-Sep-2021
  • (2020)HaRMonyProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378489(575-590)Online publication date: 9-Mar-2020
  • Show More Cited By

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cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 63, Issue 12
December 2014
270 pages

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IEEE Computer Society

United States

Publication History

Published: 01 December 2014

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Cited By

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  • (2022)Data ConvectionProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/35080276:1(1-25)Online publication date: 28-Feb-2022
  • (2021)SoftRefresh: Targeted refresh for Energy-efficient DRAM systems via Software and Operating Systems supportProceedings of the International Symposium on Memory Systems10.1145/3488423.3519323(1-6)Online publication date: 27-Sep-2021
  • (2020)HaRMonyProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378489(575-590)Online publication date: 9-Mar-2020
  • (2019)Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory ManagementACM Transactions on Design Automation of Electronic Systems10.1145/332907924:4(1-25)Online publication date: 5-Jun-2019
  • (2019)CROWProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322231(129-142)Online publication date: 22-Jun-2019
  • (2019)Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAMJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05817-935:4(485-495)Online publication date: 1-Aug-2019
  • (2018)Efficient coding scheme for DDR4 memory subsystemsProceedings of the International Symposium on Memory Systems10.1145/3240302.3240424(148-157)Online publication date: 1-Oct-2018
  • (2018)Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stressProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3236091(230-235)Online publication date: 15-Jul-2018
  • (2017)The Reach Profiler (REAPER)ACM SIGARCH Computer Architecture News10.1145/3140659.308024245:2(255-268)Online publication date: 24-Jun-2017
  • (2017)Using run-time reverse-engineering to optimize DRAM refreshProceedings of the International Symposium on Memory Systems10.1145/3132402.3132419(115-124)Online publication date: 2-Oct-2017
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