research-article

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

Authors:

Chun Jason XueAuthors Info & Claims

IEEE Transactions on Computers, Volume 64, Issue 8

Pages 2169 - 2181

https://doi.org/10.1109/TC.2014.2360527

Published: 01 August 2015 Publication History

Abstract

Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features such as high storage density and ultra low leakage power. However, long write latency and high write energy are the two challenges for STT-RAM. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data losses resulting from volatility, refresh schemes have been proposed. However, refresh operations consume additional overhead. In this paper, we propose to significantly reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed to further reduce the number of refreshes. Experimental results show that, on average, the proposed methods can reduce the number of refresh operations by 84.2 percent, and reduce the dynamic energy consumption by 38.0 percent for volatile STT-RAM caches while incurring only 4.1 percent performance degradation.

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Cited By

Park JLee MKim SJu MHong J(2019)MH CacheACM Transactions on Architecture and Code Optimization10.1145/332852016:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3328520
Khajekarimi EJamshidi KVafaei A(2019)Energy minimization in the STT-RAM-based high-capacity last-level cachesThe Journal of Supercomputing10.1007/s11227-019-02918-275:10(6831-6854)Online publication date: 1-Oct-2019
https://dl.acm.org/doi/10.1007/s11227-019-02918-2
Bi XMao MWang DLi H(2017)Cross-Layer Optimization for Multilevel Cell STT-RAM CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.266554325:6(1807-1820)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2665543
Show More Cited By

Index Terms

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 64, Issue 8

Aug. 2015

318 pages

ISSN:0018-9340

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Copyright © 2014.

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IEEE Computer Society

United States

Publication History

Published: 01 August 2015

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Cited By

Park JLee MKim SJu MHong J(2019)MH CacheACM Transactions on Architecture and Code Optimization10.1145/332852016:3(1-26)Online publication date: 18-Jul-2019
https://dl.acm.org/doi/10.1145/3328520
Khajekarimi EJamshidi KVafaei A(2019)Energy minimization in the STT-RAM-based high-capacity last-level cachesThe Journal of Supercomputing10.1007/s11227-019-02918-275:10(6831-6854)Online publication date: 1-Oct-2019
https://dl.acm.org/doi/10.1007/s11227-019-02918-2
Bi XMao MWang DLi H(2017)Cross-Layer Optimization for Multilevel Cell STT-RAM CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.266554325:6(1807-1820)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TVLSI.2017.2665543
Chen XKhoshavi NDeMara RWang JHuang DWen WChen Y(2017)Energy-Aware Adaptive Restore Schemes for MLC STT-RAM CacheIEEE Transactions on Computers10.1109/TC.2016.262524566:5(786-798)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2625245

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