research-article

A Procedure for Placement of Standard-Cell VLSI Circuits

Authors:

A. E. Dunlop,

B. W. KernighanAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 4, Issue 1

Pages 92 - 98

https://doi.org/10.1109/TCAD.1985.1270101

Published: 01 November 2006 Publication History

Abstract

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

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Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
https://dl.acm.org/doi/10.1145/3609335
Guo LMaidee PZhou YLavin CHung ELi WLau JQiao WChi YSong LXiao YKaviani AZhang ZCong J(2023)RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial ReconfigurationACM Transactions on Reconfigurable Technology and Systems10.1145/359302516:4(1-30)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1145/3593025
Guo LMaidee PZhou YLavin CWang JChi YQiao WKaviani AZhang ZCong JAdler MIenne P(2022)RapidStreamProceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3490422.3502361(1-12)Online publication date: 13-Feb-2022
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A Procedure for Placement of Standard-Cell VLSI Circuits
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 4, Issue 1

November 2006

122 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
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