research-article

Optimal Chaining of CMOS Transistors in a Functional Cell

Authors:

S. Wimer,

R. Y. Pinter,

J. A. FeldmanAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 6, Issue 5

Pages 795 - 801

https://doi.org/10.1109/TCAD.1987.1270322

Published: 01 November 2006 Publication History

Abstract

We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. We show how our method was used to compose cells in a row into a functional slice (e.g. an adder) that can be used in, say, a data path.

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Ren HFojtik M(2021)Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology NodesProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431569(684-689)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431569
Ren HFojtik M(2021)Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586188(1291-1294)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586188
Cremer PHougardy SSchneider JSilvanus JOzdal MChu C(2017)Automatic Cell Layout in the 7nm EraProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036672(99-106)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036672
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Optimal Chaining of CMOS Transistors in a Functional Cell
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 6, Issue 5

November 2006

218 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Ren HFojtik M(2021)Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology NodesProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431569(684-689)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431569
Ren HFojtik M(2021)Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586188(1291-1294)Online publication date: 5-Dec-2021
https://dl.acm.org/doi/10.1109/DAC18074.2021.9586188
Cremer PHougardy SSchneider JSilvanus JOzdal MChu C(2017)Automatic Cell Layout in the 7nm EraProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036672(99-106)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036672
Lu ALu HJang ELin YHung CChuang CLin RNebel WAtienza D(2015)Simultaneous transistor pairing and placement for CMOS standard cellsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757194(1647-1652)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757194
Gupta AHayes J(2000)CLIPACM Transactions on Design Automation of Electronic Systems10.1145/348019.3482345:3(510-547)Online publication date: 1-Jul-2000
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Guruswamy MMaziasz RDulitz DRaman SChiluvuri VFernandez AJones LYoffa EDe Micheli GRabaey J(1997)CELLERITYProceedings of the 34th annual Design Automation Conference10.1145/266021.266126(327-332)Online publication date: 13-Jun-1997
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Gupta AThe SHayes J(1996)XPRESSProceedings of the 1996 European conference on Design and Test10.5555/787259.787627Online publication date: 11-Mar-1996
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Arsintescu BSpânoche SSymonds GNebel W(1996)Global stacking for analog circuitsProceedings of the conference on European design automation10.5555/252471.252538(392-397)Online publication date: 20-Sep-1996
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Rekhi STrotter JLinder DPreas B(1995)Automatic layout synthesis of leaf cellsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217540(267-272)Online publication date: 1-Jan-1995
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Hwang CHsieh YLin YHsu YNewton A(1991)An efficient layout style for 2-metal CMOS leaf cells and their automatic generationProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127716(481-486)Online publication date: 1-Jun-1991
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Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI

Optimal Layout of CMOS Functional Arrays

A four-quadrant current multiplier/divider cell with four transistors

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