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Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits

Published: 01 October 2008 Publication History

Abstract

The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - particularly in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized as high-quality arithmetic circuits, close to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10%-20%.

Cited By

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  • (2024)ROVER: RTL Optimization via Verified E-Graph RewritingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341015443:12(4687-4700)Online publication date: 1-Dec-2024
  • (2020)LUXORProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375303(161-171)Online publication date: 23-Feb-2020
  • (2016)Flexible DSP Accelerator Architecture Exploiting Carry-Save ArithmeticIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239097424:1(368-372)Online publication date: 1-Jan-2016
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 27, Issue 10
October 2008
201 pages

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IEEE Press

Publication History

Published: 01 October 2008

Author Tags

  1. Arithmetic optimization
  2. logic synthesis
  3. term rewriting system

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Cited By

View all
  • (2024)ROVER: RTL Optimization via Verified E-Graph RewritingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341015443:12(4687-4700)Online publication date: 1-Dec-2024
  • (2020)LUXORProceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3373087.3375303(161-171)Online publication date: 23-Feb-2020
  • (2016)Flexible DSP Accelerator Architecture Exploiting Carry-Save ArithmeticIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239097424:1(368-372)Online publication date: 1-Jan-2016
  • (2014)Improving circuit performance with multispeculative additive trees in high-level synthesisMicroelectronics Journal10.1016/j.mejo.2014.06.00545:11(1470-1479)Online publication date: 1-Nov-2014
  • (2013)Multispeculative additive trees in high-level synthesisProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485337(188-193)Online publication date: 18-Mar-2013
  • (2011)Compressor tree synthesis on commercial high-performance FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/2068716.20687254:4(1-19)Online publication date: 28-Dec-2011
  • (2010)Improving FPGA performance for carry-save arithmeticIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201438018:4(578-590)Online publication date: 1-Apr-2010
  • (2009)Iterative layeringProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687547(797-804)Online publication date: 2-Nov-2009
  • (2009)An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 CompressorACM Transactions on Reconfigurable Technology and Systems10.1145/1575774.15757782:3(1-42)Online publication date: 1-Sep-2009
  • (2009)Field Programmable Compressor TreesACM Transactions on Reconfigurable Technology and Systems10.1145/1534916.15349232:2(1-36)Online publication date: 1-Jun-2009

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