research-article

Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices

Authors:

Zhiguo ShiAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 39, Issue 7

Pages 1498 - 1510

https://doi.org/10.1109/TCAD.2019.2917844

Published: 01 July 2020 Publication History

Abstract

Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well-known for their bursty workloads and limited energy storage—usually in the form of tiny batteries. To ensure battery lifetime, dynamic voltage frequency scaling (DVFS) has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, induces large <inline-formula> <tex-math notation="LaTeX">${\text {L}di}{/}{\mathrm {d}t}$ </tex-math></inline-formula> noise, thereby stressing the power delivery system (PDS). Due to the limited area and cost target, adding additional decoupling capacitance to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase/decrease the clock frequency in steps, also known as, clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this paper, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The experiments show that the optimized sequence is able to significantly mitigate noise within the desired transition time, thereby saving both power and energy.

References

[1]

P.-C. Wu, Y.-P. Kuo, C.-S. Wu, C.-T. Chuang, Y.-H. Chu, and W. Hwang, “PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems,” in Proc. SoCC, Las Vegas, NV, USA, 2014, pp. 136–139.

[2]

M. Bohr, “The new era of scaling in an SoC world,” in Proc. ISSCC, San Francisco, CA, USA, 2009, pp. 23–28.

[3]

K. Arabi, R. Saleh, and X. Meng, “Power supply noise in SoCs: Metrics, management, and measurement,” IEEE Des. Test. Comput., vol. 24, no. 3, pp. 236–244, May/Jun. 2007.

Digital Library

[4]

J.-M. Chabloz and A. Hemani, “Distributed DVFS using rationally-related frequencies and discrete voltage levels,” in Proc. ISLPED, Austin, TX, USA, 2010, pp. 247–252.

[5]

V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, “Reducing power in high-performance microprocessors,” in Proc. DAC, 1998, pp. 732–737.

[6]

A. Zomaya and Y. Lee, Energy-Efficient Distributed Computing Systems. Hoboken, NJ, USA: Wiley, 2012.

Digital Library

[7]

C. Zhuo, K. Unda, Y. Shi, and W.-K. Shih, “A novel cross-layer framework for early-stage power delivery and architecture co-exploration,” in Proc. DAC, Austin, TX, USA, 2016, pp. 1–6.

[8]

J. Balcellset al., “Frequency modulation techniques for EMI reduction in SMPS,” in Proc. PEA, Dresden, Germany, 2005, pp. 8–10.

[9]

M. K. Yadav, M. R. Casu, and M. Zamboni, “DVFS based on voltage dithering and clock scheduling for GALS systems,” in Proc. ASYNC, 2012, pp. 118–125.

[10]

S. Parket al., “Accurate modeling of the delay and energy overhead of dynamic voltage and frequency scaling in modern microprocessors,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 5, pp. 695–708, May 2013.

Digital Library

[11]

M. S. Gupta, J. L. Oatley, R. Joseph, G.-Y. Wei, and D. M. Brooks, “Understanding voltage variations in chip multiprocessors using a distributed power-delivery network,” in Proc. DATE, Nice, France, 2007, pp. 624–629.

[12]

W.-C. D. Lam, C.-K. Koh, and C.-W. A. Tsao, “Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy,” in Proc. ISQED, San Jose, CA, USA, 2003, pp. 327–332.

[13]

Y. Kimet al., “AUDIT: Stress testing the automatic way,” in Proc. ISM, Vancouver, BC, Canada, 2012, pp. 212–223.

[14]

E. Grochowski, D. Ayers, and V. Tiwari, “Microarchitectural simulation and control of di/dt-induced power supply voltage variation,” in Proc. HPCA, Cambridge, MA, USA, 2002, pp. 7–16.

[15]

D. Ma and R. Bondade, “Enabling power-efficient DVFS operations on silicon,” IEEE Circuits Syst. Mag., vol. 10, no. 1, pp. 14–30, 2010.

Digital Library

[16]

W. H. Cheng and B. M. Baas, “Dynamic voltage and frequency scaling circuits with two supply voltages,” in Proc. ISCAS, Seattle, WA, USA, 2008, pp. 1236–1239.

[17]

E. A. Burtonet al., “FIVR—Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs,” in Proc. APEC, Fort Worth, TX, USA, 2014, pp. 432–439.

[18]

Y.-J. Leeet al., “A 200-mA digital low drop-out regulator with coarse-fine dual loop in mobile application processor,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 64–76, Jan. 2017.

[19]

P. Hammarlundet al., “Haswell: The fourth-generation Intel Core processor,” IEEE Micro, vol. 34, no. 2, pp. 6–20, Mar./Apr. 2014.

[20]

S. Hall and H. Heck, Advanced Signal Integrity for High-Speed Digital Designs. Hoboken, NJ, USA: Wiley, 2009.

Digital Library

[21]

Y. Kim and L. K. John, “Automated di/dt stressmark generation for microprocessor power delivery networks,” in Proc. ISLPED, Fukuoka, Japan, 2011, pp. 253–258.

[22]

H. Zheng, B. Krauter, and L. Pileggi, “On-package decoupling optimization with package macromodels,” in Proc. CICC, San Jose, CA, USA, 2003, pp. 723–726.

[23]

J. Zhao, J. Zhang, and J. Fang, “Effects of power/ground via distribution on the power/ground performance of C4/BGA packages,” in Proc. EPEP, 1998, pp. 177–180.

[24]

T.-H. Chen and C. C.-P. Chen, “Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods,” in Proc. DAC, Las Vegas, NV, USA, 2001, pp. 559–562.

[25]

H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power grid analysis using random walks,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 8, pp. 1204–1224, Aug. 2005.

Digital Library

[26]

J. N. Kozhaya, S. R. Nassif, and F. N. Najm, “A multigrid-like technique for power grid analysis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 10, pp. 1148–1160, Oct. 2002.

Digital Library

[27]

Z. Feng and P. Li, “Multigrid on GPU: Tackling power grid analysis on parallel SIMT platforms,” in Proc. ICCAD, San Jose, CA, USA, 2008, pp. 647–654.

[28]

X.-D. S. Tan and C.-J. R. Shi, “Fast power/ground network optimization based on equivalent circuit modeling,” in Proc. DAC, Las Vegas, NV, USA, 2001, pp. 550–554.

[29]

F. N. Najm, “Overview of vectorless/early power grid verification,” in Proc. ICCAD, San Jose, CA, USA, 2012, pp. 670–677.

[30]

C. Zhuo, J. Hu, M. Zhao, and K. Chen, “Power grid analysis and optimization using algebraic multigrid,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 4, pp. 738–751, Apr. 2008.

Digital Library

[31]

P. B. Evans, S. L. Lind, and T. Dossey, “Validation of high-definition electric power delivery network simulation,” in Proc. PESG, Providence, RI, USA, 2010, pp. 1–7.

[32]

C. Zhuo, H. Gan, W.-K. Shih, and A. A. Aydiner, “A cross-layer approach for early-stage power grid design and optimization,” ACM J. Emerg. Technol. Comput. Syst., vol. 12, no. 3, pp. 1–25, 2015.

Digital Library

[33]

V. Panditet al., Power Integrity for I/O Interfaces: With Signal Integrity/Power Integrity Co-Design. Upper Saddle River, NJ, USA: Prentice-Hall, 2010.

[34]

E. Andersen and K. Andersen, “Presolving in linear programming,” Math. Program., vol. 71, no. 2, pp. 221–245, 1995.

Digital Library

[35]

S. Paulraj and P. Sumathi, “A comparative study of redundant constraints identification methods in linear programming problems,” Math. Problems Eng., vol. 2010, pp. 1–16, Sep. 2010.

[36]

B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” Bell Syst. Tech. J., vol. 49, no. 2, pp. 291–307, Feb. 1970.

[37]

C. Zhuo, G. Wilke, R. Chakraborty, A. A. Aydiner, and S. Chakravar, “Silicon-validated power delivery modeling and analysis on a 32-nm DDR I/O interface,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 9, pp. 1760–1771, Sep. 2015.

Cited By

Guo NPeng FShi JYang FTao JZeng X(2023)Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental VariationACM Transactions on Design Automation of Electronic Systems10.1145/362632129:1(1-17)Online publication date: 6-Oct-2023
https://dl.acm.org/doi/10.1145/3626321
Peng QBian JHuang ZWang SYan A(2023)A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift RegistersACM Transactions on Design Automation of Electronic Systems10.1145/361029529:1(1-17)Online publication date: 21-Jul-2023
https://dl.acm.org/doi/10.1145/3610295
Wen CWu YYin XZhuo CTakahashi A(2023)Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy EfficiencyProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567885(134-139)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567885
Show More Cited By

Index Terms

Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices
1. Hardware
  1. Hardware validation
  2. Integrated circuits

Index terms have been assigned to the content through auto-classification.

Recommendations

Noise-aware DVFS transition sequence optimization for battery-powered IoT devices
DAC '18: Proceedings of the 55th Annual Design Automation Conference

Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well known for their bursty workloads and limited energy storage --- usually in the form of tiny batteries. To ensure battery lifetime, DVFS has become ...
Noise-Aware DVFS Transition Sequence Optimization for Battery-Powered IoT Devices
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)
Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well known for their bursty workloads and limited energy storage — usually in the form of tiny batteries. To ensure battery lifetime, DVFS has ...
Latency-aware DVFS for efficient power state transitions on many-core architectures

Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (...

Comments

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 39, Issue 7

July 2020

192 pages

ISSN:0278-0070

Issue’s Table of Contents

0278-0070 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.

Publisher

IEEE Press

Publication History

Published: 01 July 2020

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

19
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Guo NPeng FShi JYang FTao JZeng X(2023)Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental VariationACM Transactions on Design Automation of Electronic Systems10.1145/362632129:1(1-17)Online publication date: 6-Oct-2023
https://dl.acm.org/doi/10.1145/3626321
Peng QBian JHuang ZWang SYan A(2023)A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift RegistersACM Transactions on Design Automation of Electronic Systems10.1145/361029529:1(1-17)Online publication date: 21-Jul-2023
https://dl.acm.org/doi/10.1145/3610295
Wen CWu YYin XZhuo CTakahashi A(2023)Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy EfficiencyProceedings of the 28th Asia and South Pacific Design Automation Conference10.1145/3566097.3567885(134-139)Online publication date: 16-Jan-2023
https://dl.acm.org/doi/10.1145/3566097.3567885
Dong XChen YChen JWang YLi JNi TShi ZYin XZhuo C(2023)Worst-case Power Integrity Prediction Using Convolutional Neural NetworkACM Transactions on Design Automation of Electronic Systems10.1145/356493228:4(1-19)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3564932
Chen YGuo ZWang RHuang RLin YZhuo C(2023)Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334260343:5(1511-1524)Online publication date: 13-Dec-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3342603
Gao DYang ZHuang QZhang GYin XLi BSchlichtmann UZhuo C(2023)BRoCoM: A Bayesian Framework for Robust Computing on Memristor CrossbarIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.321507142:7(2136-2148)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3215071
Wu YWen CYin XZhuo C(2023)LMM: A Fixed-Point Linear Mapping Based Approximate Multiplier for IoTJournal of Computer Science and Technology10.1007/s11390-023-2572-838:2(298-308)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1007/s11390-023-2572-8
Ren YWang TZhang SZhang J(2023)An intelligent big data collection technology based on micro mobile data centers for crowdsensing vehicular sensor networkPersonal and Ubiquitous Computing10.1007/s00779-020-01440-027:3(563-579)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1007/s00779-020-01440-0
Wen CDong XChen BTida UShi YZhuo C(2022)Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC ConverterACM Transactions on Design Automation of Electronic Systems10.1145/350770027:5(1-23)Online publication date: 7-Mar-2022
https://dl.acm.org/doi/10.1145/3507700
Dong XChen YYin XZhuo COshana R(2022)Worst-case dynamic power distribution network noise prediction using convolutional neural networkProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530600(1225-1230)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530600
Show More Cited By

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents