research-article

A low power and wide range programmable clock generator with a high multiplication factor

Authors:

Stephen T. Kim,

Joy LaskarAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 19, Issue 4

Pages 701 - 705

https://doi.org/10.1109/TVLSI.2009.2036433

Published: 01 April 2011 Publication History

Abstract

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18-µm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as lowas 30MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051mm².

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Cited By

Gholami M(2013)A Novel Low Power Architecture for DLL-Based Frequency SynthesizersCircuits, Systems, and Signal Processing10.1007/s00034-012-9488-932:2(781-801)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1007/s00034-012-9488-9
Assaad MAlser M(2012)Design of an all-digital synchronized frequency multiplier based on a dual-loop (D/FLL) architectureVLSI Design10.1155/2012/5462122012(17-17)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/546212

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 19, Issue 4

April 2011

200 pages

ISSN:1063-8210

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Copyright © 2011.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 April 2011

Revised: 12 September 2009

Received: 10 June 2009

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Cited By

Gholami M(2013)A Novel Low Power Architecture for DLL-Based Frequency SynthesizersCircuits, Systems, and Signal Processing10.1007/s00034-012-9488-932:2(781-801)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1007/s00034-012-9488-9
Assaad MAlser M(2012)Design of an all-digital synchronized frequency multiplier based on a dual-loop (D/FLL) architectureVLSI Design10.1155/2012/5462122012(17-17)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/546212

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