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IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

Published: 01 June 2013 Publication History

Abstract

Imbalanced distribution of workloads across a chip multiprocessor (CMP) constitutes wasteful use of resources. Most existing load distribution and balancing techniques employ very limited hardware support and rely predominantly on software for their operation. This paper introduces IsoNet, a hardware-based conflict-free dynamic load distribution and balancing engine. IsoNet is a lightweight job queue manager responsible for administering the list of jobs to be executed, and maintaining load balance among all CMP cores. By exploiting a micro-network of load-balancing modules, the proposed mechanism is shown to effectively reinforce concurrent computation in many-core environments. Detailed evaluation using a full-system simulation framework indicates that IsoNet significantly outperforms existing techniques and scales efficiently to as many as 1024 cores. Furthermore, to assess its feasibility, the IsoNet design is synthesized, placed, and routed in 45-nm VLSI technology. Analysis of the resulting low-level implementation shows that IsoNet's area and power overhead are almost negligible.

Cited By

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  • (2021)GraphPEGACM Transactions on Architecture and Code Optimization10.1145/345044018:3(1-24)Online publication date: 10-May-2021
  • (2021)DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00687-749:4(506-540)Online publication date: 1-Aug-2021
  • (2019)SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore ArchitecturesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_15(212-225)Online publication date: 7-Jul-2019
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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 21, Issue 6
June 2013
191 pages

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IEEE Educational Activities Department

United States

Publication History

Published: 01 June 2013

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Cited By

View all
  • (2021)GraphPEGACM Transactions on Architecture and Code Optimization10.1145/345044018:3(1-24)Online publication date: 10-May-2021
  • (2021)DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00687-749:4(506-540)Online publication date: 1-Aug-2021
  • (2019)SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore ArchitecturesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_15(212-225)Online publication date: 7-Jul-2019
  • (2018)The Agamid design-space exploration frameworkDesign Automation for Embedded Systems10.1007/s10617-018-9214-322:4(293-314)Online publication date: 1-Dec-2018
  • (2016)CAFProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967954(351-362)Online publication date: 11-Sep-2016

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