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Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

Published: 01 June 2015 Publication History

Abstract

The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multiplier architectures that can tradeoff computational accuracy with energy consumption at design time. Compared with a precise multiplier, the proposed multiplier can consume 58% less energy/op with average computational error of $\sim 1$ %. Finally, we demonstrate that such a small computational error does not notably impact the quality of DSP and the accuracy of classification applications.

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      Published In

      cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
      IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 23, Issue 6
      June 2015
      192 pages

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      IEEE Educational Activities Department

      United States

      Publication History

      Published: 01 June 2015

      Author Tags

      1. multiplication
      2. Approximation
      3. energy efficiency

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      • (2023)Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM InstantiationACM Transactions on Embedded Computing Systems10.1145/358073722:4(1-24)Online publication date: 25-Jan-2023
      • (2023)On the Design of Iterative Approximate Floating-Point MultipliersIEEE Transactions on Computers10.1109/TC.2022.321646572:6(1623-1635)Online publication date: 1-Jun-2023
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      • (2021)Energy Efficient Error Resilient Multiplier Using Low-power CompressorsACM Transactions on Design Automation of Electronic Systems10.1145/348883727:3(1-26)Online publication date: 17-Nov-2021
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