Fluctuations in intrinsic linear V_t, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic σV_T, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.

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Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
1. Hardware
  1. Integrated circuits
  2. Robustness

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ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

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ISBN:1595931376

DOI:10.1145/1077603

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Purdue University
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Vivek Tiwari
Intel

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