Article

Compiler-guided register reliability improvement against soft errors

Authors:

Jun Yan,

Wei ZhangAuthors Info & Claims

EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded software

Pages 203 - 209

https://doi.org/10.1145/1086228.1086266

Published: 18 September 2005 Publication History

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Abstract

With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely used in reliability-sensitive environments, it becomes increasingly important to develop cost-effective techniques to improve the processor reliability against soft errors. This paper focuses on studying the register file immunity against soft errors since modern processors typically employ a large number of registers, which are accessed very frequently. As a result, soft errors occurred in registers can easily propagate to functional units or the memory system, leading to silent data error (SDC) or system crash.To develop cost-effective techniques to fight soft errors for embedded processors, the first step is to understand the register file susceptibility to soft errors and its impact on the system reliability accurately. Toward this goal, this paper proposes the concept of register vulnerability factor (RVF) to characterize the probability that register transient errors can escape the register file and thus potentially impact the system reliability. Built upon the RVF concept, we then propose two cost-effective compiler-guided techniques to improve the register file reliability by lowering the RVF value. Our experiments indicate that on average, the RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly while protecting register files against transient errors.

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Cited By

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Ko YBurgstaller BGrosser TDubach CSteuwer MXue JOttoni GQuintão Pereira F(2024)BEC: Bit-Level Static Analysis for Reliability against Soft ErrorsProceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO57630.2024.10444844(283-295)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1109/CGO57630.2024.10444844
Ozturk ZTopcuoglu HKandemir M(2022)Studying error propagation on application data structure and hardwareThe Journal of Supercomputing10.1007/s11227-022-04625-x78:17(18691-18724)Online publication date: 13-Jun-2022
https://doi.org/10.1007/s11227-022-04625-x
Ozturk ZTopcuoglu HKandemir M(2022)Quantifying the impact of data replication on error propagationCluster Computing10.1007/s10586-022-03726-926:3(1985-1999)Online publication date: 13-Sep-2022
https://doi.org/10.1007/s10586-022-03726-9
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Index Terms

Compiler-guided register reliability improvement against soft errors
1. Hardware
  1. Hardware test
  2. Robustness

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Reviews

Reviewer: Juan A. Carrasco

As the size of processors shrinks, transient errors caused by external particle strikes, also known as soft errors, are becoming a significant source of system failures. This paper analyzes the impact of such soft errors in the register file of a typical microprocessor with a very long instruction word (VLIW) architecture. It also analyzes the effectiveness of three compiler-based techniques aimed at reducing the impact of soft errors in the register file. The analyzed processor includes four integer arithmetic logic units (ALUs), two floating point ALUs, one load/store unit, one branch unit, and a register file with 64 registers. The analysis is performed using ten benchmark applications. The impact of soft errors is measured using a new metric, the register vulnerability factor (RVF), defined as the probability that a soft error in the file register will be propagated to other hardware elements. The RVF metric can be easily estimated by simulation. The three compiler-based techniques for reducing the RVF include instruction rescheduling (advancing read operations and delaying write operations), register reassignment (some registers are protected by an error correcting code (ECC), and the registers showing higher RVF are reassigned to them); and a hybrid technique combining the first two techniques. Simulation experiments show that instruction rescheduling reduces the RVF to a value of 9.1 percent, on average; register reassignment with four ECC-protected registers reduces RVF to an average of 10.5 percent; and the hybrid technique with four ECC-protected registers reduces the RVF to a value of 6.1 percent, on average. The simulation results reported in the paper are interesting. The authors also report results from previous experiments analyzing the impact of soft errors in microprocessors. Online Computing Reviews Service

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Published In

EMSOFT '05: Proceedings of the 5th ACM international conference on Embedded software

September 2005

390 pages

ISBN:1595930914

DOI:10.1145/1086228

Conference Chair:
Wayne Wolf
Princeton University, Princeton, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 September 2005

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EMSOFT05

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EMSOFT05: Fifth ACM International Conference on Embedded Software 2005

September 18 - 22, 2005

NJ, Jersey City, USA

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Overall Acceptance Rate 60 of 203 submissions, 30%

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Cited By

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Ko YBurgstaller BGrosser TDubach CSteuwer MXue JOttoni GQuintão Pereira F(2024)BEC: Bit-Level Static Analysis for Reliability against Soft ErrorsProceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO57630.2024.10444844(283-295)Online publication date: 2-Mar-2024
https://dl.acm.org/doi/10.1109/CGO57630.2024.10444844
Ozturk ZTopcuoglu HKandemir M(2022)Studying error propagation on application data structure and hardwareThe Journal of Supercomputing10.1007/s11227-022-04625-x78:17(18691-18724)Online publication date: 13-Jun-2022
https://doi.org/10.1007/s11227-022-04625-x
Ozturk ZTopcuoglu HKandemir M(2022)Quantifying the impact of data replication on error propagationCluster Computing10.1007/s10586-022-03726-926:3(1985-1999)Online publication date: 13-Sep-2022
https://doi.org/10.1007/s10586-022-03726-9
Rocha da Rosa FOst LReis RRocha da Rosa FOst LReis R(2020)Background on Soft ErrorsSoft Error Reliability Using Virtual Platforms10.1007/978-3-030-55704-1_2(9-17)Online publication date: 3-Nov-2020
https://doi.org/10.1007/978-3-030-55704-1_2
Ramos AUllah AReviriego PMaestro J(2018)Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAsIEEE Transactions on Computers10.1109/TC.2017.273799667:2(299-304)Online publication date: 1-Feb-2018
https://doi.org/10.1109/TC.2017.2737996
Psychou GRodopoulos DSabry MGemmeke TAtienza DNoll TCatthoor F(2017)Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital SystemsACM Computing Surveys10.1145/309269950:4(1-38)Online publication date: 4-Oct-2017
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Ghaffarian SShahriari H(2017)Software Vulnerability Analysis and Discovery Using Machine-Learning and Data-Mining TechniquesACM Computing Surveys10.1145/309256650:4(1-36)Online publication date: 25-Aug-2017
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Keiren JFontana PCleaveland R(2017)Corrections to “A Menagerie of Timed Automata”ACM Computing Surveys10.1145/307880950:3(1-8)Online publication date: 29-Jun-2017
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Poh GChin JYau WChoo KMohamad M(2017)Searchable Symmetric EncryptionACM Computing Surveys10.1145/306400550:3(1-37)Online publication date: 26-May-2017
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Gomes HBarddal JEnembreck FBifet A(2017)A Survey on Ensemble Learning for Data Stream ClassificationACM Computing Surveys10.1145/305492550:2(1-36)Online publication date: 27-Mar-2017
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Recommendations

A compiler optimization to reduce soft errors in register files

On the exploitation of narrow-width values for improving register file reliability

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