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Word level functional coverage computation

Author:

Bijan AlizadehAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 7 - 12

https://doi.org/10.1145/1118299.1118304

Published: 24 January 2006 Publication History

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Abstract

This paper proposes a word-level coverage metric to determine the completeness of a set of properties verified by a word-level method. An algorithm is presented to compute a functionality based coverage metric for a sequence property as specification. Control, intermediate and output signals are represented by a multiplexer based structure of linear integer equations, and RT level properties are directly applied to this representation. A set of integer equations are symbolically simulated based on the specified property in a predictable time. We used a canonical form of linear Taylor Expansion Diagram.

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Gomez-Prado DRen QCiesielski MGuillot JBoutillon EBenini LDe Micheli GAl-Hashimi BMueller W(2009)Optimizing data flow graphs to minimize hardware implementationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874649(117-122)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874649
Ciesielski MGomez-Prado DRen QGuillot JBoutillon E(2009)Optimization of data-flow computations using canonical TED representationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202470828:9(1321-1333)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2024708
Gomez-Prado DRen QCiesielski MGuillot JBoutillon E(2009)Optimizing data flow graphs to minimize hardware implementation2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090643(117-122)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090643

Index Terms

Word level functional coverage computation
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Interconnect
      1. Input / output circuits
2. Theory of computation
  1. Computational complexity and cryptography
    1. Problems, reductions and completeness

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ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

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IEEE Press

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Published: 24 January 2006

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Gomez-Prado DRen QCiesielski MGuillot JBoutillon EBenini LDe Micheli GAl-Hashimi BMueller W(2009)Optimizing data flow graphs to minimize hardware implementationProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874649(117-122)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874649
Ciesielski MGomez-Prado DRen QGuillot JBoutillon E(2009)Optimization of data-flow computations using canonical TED representationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202470828:9(1321-1333)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2024708
Gomez-Prado DRen QCiesielski MGuillot JBoutillon E(2009)Optimizing data flow graphs to minimize hardware implementation2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090643(117-122)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090643

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